SLVAFW3B March   2025  – October 2025 AM62L , TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Management IC (PMIC) Overview
  6. 3Low Power Modes and Power Supply Optimization
    1. 3.1 PDN#1: Optimized Power Design for BOM Size and Cost
    2. 3.2 PDN#2: Optimized Power Design for Lowest Suspend Power
    3. 3.3 PDN#3: Fully Flexible Power Design
    4. 3.4 PDN#4: Power Supply Implementation for DDR4
  7. 4Power-Up Sequence
  8. 5Power-Down Sequence
  9. 6Summary
  10. 7References
  11.   A Appendix A: Discrete Power Implementation for PDN#1
  12.   B Revision History

A Appendix A: Discrete Power Implementation for PDN#1

This section describes the discrete power implementation for PDN#1. The Optimized Power Solution for BOM size and cost can also be implemented using discrete components with attributes equivalent to the devices listed below. Figure 8-1 shows an example supply diagram for a 5V input supply and LPDDR4 use case.

  • VDD_CORE (0.75V): TPS62A02
  • VDDS_DDR (1.1V): TPS62A01
  • VDDSHV (3.3V IO / 1.8V IO)
    • if total current > 500mA: TPS62A01 (DCDC)
    • if total current < 500mA: TPS74501 (LDO)
  • VDDA (1.8V analog): LP5912 (low noise LDO)
Note: This discrete PDN is an example supply implementation and has not been tested or validated by TI.
PDN Optimized for BOM Size and Cost - Discrete Implementation Figure A-1 PDN Optimized for BOM Size and Cost - Discrete Implementation
Note: The power-switch connected to VDDA_3P3_SDIO is optional and only needed if the application uses SD card. The VPP 1.8V LDO is optional and only needed if on-board eFuse programming is required.
Discrete BOM Example Figure A-2 Discrete BOM Example

A proper logic implementation is required to meet the SoC sequencing requirements and reset architecture. Figure 8-3 shows an example using LM3380 sequencer and a 6 channel open-drain buffer. The connections highlighted in orange represent the power-good signals of the devices that supply the SoC rails and the system power.

Logic Implementation - Example Figure A-3 Logic Implementation - Example