SLVAFW3B March   2025  – October 2025 AM62L , TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Management IC (PMIC) Overview
  6. 3Low Power Modes and Power Supply Optimization
    1. 3.1 PDN#1: Optimized Power Design for BOM Size and Cost
    2. 3.2 PDN#2: Optimized Power Design for Lowest Suspend Power
    3. 3.3 PDN#3: Fully Flexible Power Design
    4. 3.4 PDN#4: Power Supply Implementation for DDR4
  7. 4Power-Up Sequence
  8. 5Power-Down Sequence
  9. 6Summary
  10. 7References
  11.   A Appendix A: Discrete Power Implementation for PDN#1
  12.   B Revision History

2 Power Management IC (PMIC) Overview

The TPS65214 PMIC contains five regulators; 3 Buck regulators and 2 Low Drop-out Regulators (LDOs). The Buck converters are capable of supporting up to 2A for Buck1, and 1A each for the remaining buck regulators. LDO1 can support a maximum output current of 300mA, and LDO2 can support a maximum output current of 500mA. Both LDOs can also be configured as load switches. With a VIN range of 2.5V to 5.5V, the PMIC can support a common 3.3V or 5V system voltage. Figure 2-1 shows a summary of the voltage and current capabilities for each of the analog resources. With an I2C interface, two GPIO pins, and three multi-function pins, the TPS65214 PMIC provides the full power package to supply the AM62L SoC and the principal peripherals.

There are different orderable part numbers (OPNs) of the TPS65214 device with unique OTP settings to support different application use cases. Each TPS65214 device is distinguished by the part number and TI_DEV_ID / NVM_ID register fields. Digits #9-10 of the part number represent the default OTP configuration. For example, TPS6521401 has unique OTP settings to support the voltage and sequencing requirements of the AM62L SoC.

Note: TPS6521401 is used in the AM62L EVM
TPS65214 Functional Block DiagramFigure 2-1 TPS65214 Functional Block Diagram