SLVAFW3B March   2025  – October 2025 AM62L , TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Management IC (PMIC) Overview
  6. 3Low Power Modes and Power Supply Optimization
    1. 3.1 PDN#1: Optimized Power Design for BOM Size and Cost
    2. 3.2 PDN#2: Optimized Power Design for Lowest Suspend Power
    3. 3.3 PDN#3: Fully Flexible Power Design
    4. 3.4 PDN#4: Power Supply Implementation for DDR4
  7. 4Power-Up Sequence
  8. 5Power-Down Sequence
  9. 6Summary
  10. 7References
  11.   A Appendix A: Discrete Power Implementation for PDN#1
  12.   B Revision History

3.2 PDN#2: Optimized Power Design for Lowest Suspend Power

The Power Delivery Network (PDN) described in this section is optimized for the lowest suspend power and supports all low power modes except RTC only mode. The PDN uses a 3.5mm x 3.5mm PMIC and an external 3.3V discrete regulator to supply all the SoC power domains. This PDN is recommended for applications using RTC + IO + DDR low power mode or requiring more than 500mA current on the 3.3V IO. This PDN is designed to turn-OFF VDD_CORE and VDDA when entering RTC + IO + DDR low power mode to reduce power consumption. Figure 3-4 shows the PMIC implementation using TPS6521401 configuration.

Highlights:

  • Uses TPS6521401 PMIC. This PMIC configuration is used in the AM62L EVM. Hardware design files available.
  • Estimated BOM size for 3.3V input supply (PMIC + 3.3V power-switch): 41.69mm2 (does not include PCB clearance). Power-switch example: TPS22954.
  • Estimated BOM size for 4V-5V input supply (PMIC + 3.3V Buck): 58.68mm2 (does not include PCB clearance). Buck example: TPS62A01.
  • External 3.3V discrete is scalable based on the total current needed for 3.3V IO (including SoC + peripherals).

AM62L PDN Optimized for Lowest Suspend Power Figure 3-4 AM62L PDN Optimized for Lowest Suspend Power
Note: The power-switch connected to VDDA_3P3_SDIO is optional and only needed if the application uses SD card. The VPP 1.8V LDO is optional and only needed if on-board eFuse programming is required.

Figure 3-5 shows the digital connections between SoC and PMIC for PDN#2. The image also shows the digital signals that require external pull-up resistors. The PMIC enable pin (EN/PB/VSENSE) can be driven with the power-good signal of the pre-regulator. Alternatively, this signal can be pulled up to PMIC_VSYS if the pre-regulator does not integrate a power-good signal. The PMIC nRSTOUT and the power-good signal of the 3.3V IO drives the main SoC reset (PORz). PMIC GPO is configured to act as the power-good signal of the RTC rails (BUCK2 and LDO2) and drives the RTC power-on reset (RTC_PORz). The PMIC_LPM_EN0 drives the PMIC MODE/STBY pin to pull PORz low and turn-off VDD_CORE (BUCK1) as well as VDDA (LDO1) when entering "RTC + IO + DDR" low power modes.

SoC - PMIC Digital Connections for PDN#2 Figure 3-5 SoC - PMIC Digital Connections for PDN#2
Note: PMIC_LPM_EN0 does not require an external pull-up resistor; The SoC has an internal pullup resistor that drives the signal high if VDDS_RTC is powered. PORz is 3.3V tolerant and the external pull-up resistor can be connected to a 1.8V supply or 3.3V supply as long as VDDS_OSC0 is powered.
Table 3-2 TPS6521401 Digital Config
OTP Config Polarity
EN/PB/VSENSE Configured as Enable
  • High: PMIC executes power-on sequence.
  • Low: PMIC executes power-down sequence.
MODE/STBY Mode and Standby
  • High: PMIC in Active state. All rails enabled. Bucks operate in forced-PWM.
  • Low: PMIC in Standby state. Buck1 and LDO1 are turned-OFF. Bucks operate in auto-PFM.
GPIO/nWAKEUP Open-drain GPO
  • Configured to act as the power-good signal of Buck2 and LDO2. This digital pin drives RTC_PORz and stays high/Z when PMIC enters Standby state to support the AM62L RTC+DDR low power mode.
GPIO/VSEL Open-drain GPO
  • Configured to enable/disable external 3.3V discrete device.
Note: Refer to the TPS6521401 Technical Reference Manual to access the full list of default PMIC OTP register settings.