The Power Delivery Network (PDN) described in this section offers a flexible PMIC + discrete power design that allows supporting all the SoC low power modes. This PDN supports RTC only low power mode by isolating VDDS_RTC (1.8V) and VDD_RTC (0.75V) from the remaining power rails. Supplying the RTC domain with always-ON discrete devices allows to significantly reduce power consumption during RTC only low power mode by turning-OFF the entire PMIC and the external 3.3V discrete while only keeping the RTC rails ON. When entering RTC only low power mode, the AM62L PMIC_LPM_EN signal drives the PMIC enable pin low. Figure 3-6 shows the PMIC + discrete power implementation.

Highlights:

• This PDN can be implemented with the TPS6521401 PMIC (PMIC OTP configuration used in the AM62L EVM).
• Supports all AM62L low power modes.
• BOM size is highly dependent on the selected discrete devices for the RTC rails and the 3.3 IO.
• When using 3.3V input supply (lower power consumption), external 3.3V power switch is used. Example IC: TPS22954.
• When using 4V-5V input supply, external 3.3V DCDC is used. Example IC: TPS62A01.
• External 3.3V discrete current rating is scalable based on the total current needed for 3.3V IO.

Figure 3-6 AM62L Fully Flexible PDN

Figure 3-7 shows the digital connections between SoC and PMIC for PDN#3. The image also shows the digital signals that require external pull-up resistors. The SoC PMIC_LPM_EN0 drives the PMIC enable pin (EN/PB/VSENSE) to turn-OFF the PMIC when entering RTC only low power mode. The combined power-good signals of the discrete LDOs that supply the RTC rails drive RTC_PORz. Additionally, an open-drain buffer between the two power-on resets allows to pull the PORz low and keep the SoC in reset if a fault is detected on the external discrete LDOs. The PMIC nRSTOUT, the power-good signal of the 3.3V IO and the output of the open-drain buffer drive the main SoC reset (PORz).

Figure 3-7 SoC - PMIC Digital Connections for PDN#3