SLVAFX6 February   2026 TPS61287

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Introduction of TPS61287
    2. 1.2 Design with the Paralleled TPS61287
    3. 1.3 Synchronization Function
    4. 1.4 Phase Delay Details
  5. 2Bench Performance of TPS61287 in Parallel
    1. 2.1 Thermal Performance
    2. 2.2 Switching Waveform
    3. 2.3 Ripple Waveform
    4. 2.4 Efficiency
  6. 3Summary
  7. 4References

1.4 Phase Delay Details

The synchronization delay time is defined as the time delay between rising edge of the synchronization signal and the rising edge of the generated SW rising edge.

Table 1-1 Delay Time and Phase Related with Duty Cycle
Duty Cycle delay time delay phase
10% 2.01us 64.3%
20% 1.89us 60.5%
30% 1.78us 57.0%
40% 1.71us 54.7%
50% 1.66us 53.1%
60% 1.68us 53.8%
70% 1.66us 53.1%
80% 1.65us 52.8%
90% 1.64us 52.5%

Table 2-2 lists the estimated typical delay time and delay phase related with the duty cycle. TPS61287 has carefully designed to make about 50% of the phase delay in most cases.

In this design, SW signal voltage is used as the SYNC signal with a resistor divide. The actual phase shift is just around 50%.