SLVAFX6 February   2026 TPS61287

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Introduction of TPS61287
    2. 1.2 Design with the Paralleled TPS61287
    3. 1.3 Synchronization Function
    4. 1.4 Phase Delay Details
  5. 2Bench Performance of TPS61287 in Parallel
    1. 2.1 Thermal Performance
    2. 2.2 Switching Waveform
    3. 2.3 Ripple Waveform
    4. 2.4 Efficiency
  6. 3Summary
  7. 4References

1.2 Design with the Paralleled TPS61287

Figure 1-1 shows the schematic of two TPS61287s working in parallel. The VIN, VOUT, FB and COMP pins of the two devices are connected together.

The M/SYNC of the host device is connected to ground. The M/SYNC of the subordinate device can either connect to the DRV pin or the SW of the host device through a RC divider. TI recommends using forced PWM mode for a better current balance and reliable phase shifting.

TPS61287 Paralleled Schematic for High Power Application Figure 1-1 TPS61287 Paralleled Schematic for High Power Application