4 Results

The x in Table 4-1 and Table 4-2 indicates where the device begins to go into thermal shutdown. Capacitors higher than that can be fully charged but only after the device auto-retries several times. For some users, the output turning on and off multiple times before fully charging the capacitive load can be inefficient and timely for certain applications. Figure 4-1 shows an example waveform during normal operation where the capacitor is charged without encountering a thermal fault.

As the current limit decreases, the amount of capacitance that can be charged with the switch increases. In some cases, when charging large capacitors while utilizing a lower current limit where thermal shutdown occurs but the output is successfully charged, the VOUT curve looks more like a step function as shown in Figure 4-2. In other cases, where a higher current limit is utilized, the output voltage is not able to charge to VS as shown in Figure 4-3 regardless of the time period. The higher the inrush or load current, the more the power dissipation over the FET. The faster the device heats up, the more quickly the device reaches the thermal shutdown threshold. By configuring the device to a lower current limit, the device heats up less and recovers faster, slowly charging the large capacitor in small steps.

Be careful of slight inaccuracies due to minor voltage offsets with the measuring equipment, which also can affect the total charge time. Expect that large capacitors take more time to charge relative to small ones and that the time takes longer for those same capacitors to charge at higher temperatures. For these results, the capacitor was considered fully charged once the output voltage reached approximately 46-48V. This was based on where the output voltage stopped increasing. At the same voltage point, the current can also take slightly longer to stabilize at the load current level where only the resistive load is drawing current. The data tables show approximate charging times for the devices tested and can vary across process, voltage, and temperature (PVT) and with board layout (if not using an EVM). The key concept here is recognizing at which capacitance the device begins to experience a thermal fault.

At higher drain to source voltages, such as 48V and with higher inrush or load currents, the point where the device limits current can be higher than the target limit. This is because there is more power dissipation over the FET. The power FET heats up more relative to the current limit sense FET because there is much less current going through – I_LOAD/K_CL (current mirror mechanism). Eventually, due to mutual heating, the power FET causes the sense FET to start heating up so the two FETs get closer in temperature. Over time, the device is able to better regulate the current. This does not affect the reliability of the device.