SLVAG18 April 2025 TPSI3100 , TPSI3100-Q1
At power-up while EN is low, TPSI3133 receives power and begins to transfer power to its secondary rails (VDDM and VDDH). The internal MOSFET pulls down the comparator input to avoid a false trigger. Once EN goes high, the two current paths (paths 1 and 2) compete to set the comparator input voltage as shown in Figure 2-1. Since Path 1 normally would be faster than path 2 due to IGBT turn-on delay, once EN goes high, the TPSI3133 keeps the comparator input pulled down for an additional 100ns, allowing the IGBT to fully turn on before fault detection. Adding blanking capacitance (CBLK) can provide additional delay but must be carefully selected in order to minimize stress time. During an overload condition, the IGBT VCE rises, which brings up the voltage at the HV diode anode, trips the fault comparator threshold. Once the TPSI3133 detects the fault, it shuts off the driver which turns off the IGBT, protecting the system.
Figure 2-1 DESAT KVL Paths