SLVK181 January   2025 DRV8351-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB)
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References

1 Introduction

The DRV8351-SEP is a radiation-hardness-assured (RHA) 40V three half-bridge gate drivers, capable of driving high-side and low-side N-channel power MOSFETs. The DRV8351-SEP generates the correct gate drive voltages using an integrated bootstrap diode and external capacitor for the highside MOSFETs. GVDD is used to generate gate drive voltage for the low-side MOSFETs. The Gate Drive architecture supports peak up to 750mA source and 1.5A sink currents. The driver features:

  • Absolute Maximum Voltage ratings
    • PVDD = 40V
    • GVDD = 15V
  • Approximately 125ns propagation delay
  • Approximately 4.0ns high-side and low-side matching
  • 3x and 6x PWM Mode
    • 3x PWM allows for outputs to be controlled by dedicated input
    • PWM allows for two complementary outputs signals to be generated from single input

    • 6x PWM requires all INH and INL inputs to be supplied

3x PWM mode the user also has the ability to enable or disable the turn-on of both outputs when both inputs are on simultaneously (interlock protection). This gives the driver the ability to be used in multiple converter configurations.

The device is offered in a 20-pin plastic package. General device information and test conditions are listed in Table 1-1. For more detailed technical specifications, user guides, and application notes, see theDRV8351-SEP product pages.

Table 1-1 Overview Information
Description(1)Device Information
TI part numberDRV8351-SEP
Orderable number

DRV8351DMPWTSEP, DRV8351DIMPWTSEP

Device function40V Three Phase Half-Bridge Gate driver
TechnologyLBC9 (Linear BiCMOS 9)
Exposure facility Radiation Effects Facility, Cyclotron Institute, Texas A&M University (15 MeV / nucleon)
Heavy ion fluence per run1.0 × 106 – 1.5 × 107 ions / cm2
Irradiation temperature25°C (for SEB), 25°C (for SET testing), and 125°C (for SEL testing)
(1) TI may provide technical, applications or design advice, quality characterization, and reliability data or service, providing these items shall not expand or otherwise affect TI's warranties as set forth in the Texas Instruments Incorporated Standard Terms and Conditions of Sale for Semiconductor Products and no obligation or liability shall arise from Semiconductor Products and no obligation or liability shall arise from TI's provision of such items.