SLVK199 August 2025 TPS7H3024-SP
The TPS7H3024-SP is fabricated in the TI Linear BiCMOS 250nm process with a back-end-of-line (BEOL) stack consisting of four levels of standard thickness aluminum. The total stack height from the surface of the passivation to the silicon surface is 11.44μm based on nominal layer thickness as shown in Figure 5-1.
Accounting for energy loss through the degrader, copper foil, beam port window, air gap, and the BEOL stack of the TPS7H3024-SP, the effective LET (LETEFF) at the surface of the silicon substrate and the range was determined with:
The results are shown in Table 5-1.
Facility | Beam Energy (MeV/nucleon) | Ion Type | Degrader Steps (#) | Degrader Angle (°) | Copper Foil Width (μm) | Beam Port Window | Air Gap (mm) | Angle of Incidence | LETEFF (MeV·cm2/mg) | Range in Silicon (μm) |
|---|---|---|---|---|---|---|---|---|---|---|
TAMU | 15 | 165Ho | 0 | 0 | - | 1-mil Aramica | 40 | 0 | 75 | 95.7 |
KSEE | 19.5 | 169Tm | - | - | 5 | 3-mil PEN | 60 | 0 | 75.1 | 89.8 |