SLVSCP3D January   2015  – November 2025 TPS7B4253-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Short Circuit and Overcurrent Protection
      2. 6.3.2 Integrated Inductive Clamp Protection
      3. 6.3.3 OUT Short to Battery and Reverse Polarity Protection
      4. 6.3.4 Undervoltage Shutdown
      5. 6.3.5 Thermal Protection
      6. 6.3.6 Regulated Output (OUT)
      7. 6.3.7 Enable (EN)
      8. 6.3.8 Adjustable Output Voltage (FB and ADJ)
        1. 6.3.8.1 OUT Voltage Equal to the Reference Voltage
        2. 6.3.8.2 OUT Voltage Higher Than Reference Voltage
        3. 6.3.8.3 Output Voltage Lower Than Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation With VIN < 4V
      2. 6.4.2 Operation With EN Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application With Output Voltage Equal to the Reference Voltage
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input Capacitor
          2. 7.2.1.2.2 Output Capacitor
        3. 7.2.1.3 Application Curve
      2. 7.2.2 High-Side Switch Configuration
      3. 7.2.3 High Accuracy LDO
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation and Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

6.3.3 OUT Short to Battery and Reverse Polarity Protection

The TPS7B4253-Q1 device can withstand a short to battery, as shown in Figure 6-1. Therefore, no damage to the device occurs.

TPS7B4253-Q1 OUT Short to Battery, VIN = V(BAT)Figure 6-1 OUT Short to Battery, VIN = V(BAT)

A short to the battery can also occur when the device is powered by an isolated supply at lower voltage, as shown in Figure 6-2. In this case, the TPS7B4253-Q1 supply-input voltage is set to 7V when a short to battery (14V typical) occurs on the OUT pin which operates at 5V. The internal back-to-back PMOS remains on for 1ms, during which the input voltage of the TPS7B4253-Q1 device charges up to the battery voltage. A diode connected between the output of the dc-dc converter and the input of the TPS7B4253-Q1 device is required in case the other loads connected behind the dc-dc converter cannot withstand the voltage of an automotive battery. To achieve a lower dropout voltage, TI recommends using a Schottky diode. This diode can be eliminated if the output of the dc-dc converter and the loads the converter powers, are able to withstand automotive battery voltage.

The internal back-to-back PMOS is switched to OFF when reverse polarity or a short to battery occurs for 1ms. After that, the reverse current flows out through the IN pin with less than 10µA. Meanwhile, a special ESD structure implemented at the input helps the device withstand –40V.

TPS7B4253-Q1 OUT Short to Battery, VIN < V(BAT)Figure 6-2 OUT Short to Battery, VIN < V(BAT)

In most cases, the output of the TPS7B4253-Q1 device is shorted to the battery through an automotive cable. The parasitic inductance on the cable results in LC oscillation at the output of the TPS7B4253-Q1 device when the short to battery occurs. Ideally, the peak voltage at the output of the TPS7B4253-Q1 device must be lower than the absolute-maximum voltage rating (45 V) during LC oscillation.