SLVSCP3D January   2015  – November 2025 TPS7B4253-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Short Circuit and Overcurrent Protection
      2. 6.3.2 Integrated Inductive Clamp Protection
      3. 6.3.3 OUT Short to Battery and Reverse Polarity Protection
      4. 6.3.4 Undervoltage Shutdown
      5. 6.3.5 Thermal Protection
      6. 6.3.6 Regulated Output (OUT)
      7. 6.3.7 Enable (EN)
      8. 6.3.8 Adjustable Output Voltage (FB and ADJ)
        1. 6.3.8.1 OUT Voltage Equal to the Reference Voltage
        2. 6.3.8.2 OUT Voltage Higher Than Reference Voltage
        3. 6.3.8.3 Output Voltage Lower Than Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation With VIN < 4V
      2. 6.4.2 Operation With EN Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application With Output Voltage Equal to the Reference Voltage
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input Capacitor
          2. 7.2.1.2.2 Output Capacitor
        3. 7.2.1.3 Application Curve
      2. 7.2.2 High-Side Switch Configuration
      3. 7.2.3 High Accuracy LDO
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation and Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

4 Pin Configuration and Functions

TPS7B4253-Q1 DDA PowerPAD Package,8-Pin HSOIC With External Thermal Pad (Top View)
NC — No internal connection
Figure 4-1 DDA PowerPAD Package,8-Pin HSOIC With External Thermal Pad (Top View)
TPS7B4253-Q1 PWP Package, 20-Pin HTSSOP With Exposed Thermal Pad (Top View)
NC — No internal connection
Figure 4-2 PWP Package, 20-Pin HTSSOP With Exposed Thermal Pad (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME HSOIC PowerPAD HTSSOP
ADJ 5 11 I Connect the reference to this pin. A low signal disables the device and a high signal enables the device. The reference voltage can be connected directly or by a voltage divider for lower output voltages. To compensate for line influences, connect a capacitor close to the device pins.
EN — 19 I This pin is the enable pin. The device goes to the STANDBY state when the enable pin goes lower than the threshold value.
FB 4 10 I This pin is the feedback pin, which can connect to the external resistor divider to select the output voltage.
GND 3 6 G Ground reference
6 15
IN 8 20 I This pin is the device supply. To compensate for line influences, connect a capacitor close to the device pins.
NC 2 2-5, 7-9 NC Not connected
7 12-14, 16-18
OUT 1 1 O Block to GND with a capacitor close to the device pins that meets the capacitance and ESR requirements listed in the Section 7.2.1.2.2 section.
Exposed thermal pad — Connect the thermal pad to the GND pin or leave the pad floating.
(1) I = input, O = output, G = ground, NC = no connect