SLVSCP3D January 2015 – November 2025 TPS7B4253-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VI(UVLO) | IN undervoltage detection | VIN rising | 3.65 | V | |||
| VIN falling | 2.8 | V | |||||
| ΔVO | Output voltage tracking accuracy(1) | IOUT
= 100µA to 300mA, VIN = 4 to 40V VADJ < VIN – 1V 1.5V < VADJ < 18V for HTSSOP 2V < VADJ < 18V for SO PowerPAD | –4 | 4 | mV | ||
| ΔVO(ΔIO) | Load regulation steady-state | IOUT = 0.1 to 300mA, VADJ= 5V | 4 | mV | |||
| ΔVO(ΔVI) | Line regulation steady-state | IOUT= 10mA, VIN = 6 to 40V, VADJ = 5V | 4 | mV | |||
| PSRR | Power supply ripple rejection | ƒrip = 100Hz, Vrip = 0.5VPP, C(OUT) = 10µF, IOUT = 100mA | 70 | dB | |||
| V(DROPOUT) | Dropout voltage (V(DROPOUT) = VIN – VOUT) | IOUT = 200mA, VIN = VADJ ≥ 4V(2) | 320 | 520 | mV | ||
| IO(lim) | Output current limitation | VADJ = 5V, OUT short to GND | 301 | 450 | 520 | mA | |
| IR(IN) | Reverse current at IN | VIN = 0V, VOUT = 40V, VADJ = 5V | –2 | 0 | µA | ||
| IR(–IN) | Reverse current at negative IN | VIN = –40V, VOUT = 0V, VADJ = 5V | –10 | 0 | µA | ||
| TSD | Thermal shutdown temperature | TJ increases because of power dissipation generated by the IC | 175 | °C | |||
| TSD_hys | Thermal shutdown hysteresis | 15 | °C | ||||
| IQ | Current consumption | 4V ≤ VIN ≤ 40V, VADJ = 0V; VEN = 0V | 2 | 4 | µA | ||
| 4V ≤ VIN ≤ 40V, VEN ≥ 2V, VADJ < 0.8V | 7 | 18 | |||||
| 4V ≤ VIN ≤ 40V, IOUT < 100µA, VADJ = 5V | 60 | 100 | |||||
| 4V ≤ VIN ≤ 40V, IOUT < 300mA, VADJ = 5V | 350 | 400 | |||||
| IQ(DROPOUT) | Current consumption in dropout region | VIN = VADJ = 5V, IOUT = 100µA | 70 | 140 | µA | ||
| II(ADJ) | Adjust input current | VADJ = VFB = 5V | HTSSOP package | 0.5 | µA | ||
| SO PowerPAD package | 5.5 | ||||||
| V(ADJ_LOW) | Adjust low signal valid | VOUT = 0V | HTSSOP package | 0 | 0.8 | V | |
| SO PowerPAD package | 0 | 0.7 | |||||
| V(ADJ_HIGH) | Adjust high signal valid | |VOUT – VADJ| < 4mV | HTSSOP package | 1.5 | 18 | V | |
| SO PowerPAD package | 2 | 18 | |||||
| V(EN_LOW) | Enable low signal valid | VOUT = 0V | 0 | 0.7 | V | ||
| V(EN_HIGH) | Enable high Signal Valid | OUT settled | 2 | 40 | V | ||
| IEN | Enable pulldown current | 2V < VEN < 40V | 5 | µA | |||
| IFB | FB bias current | VADJ = VFB = 5V | 0.5 | µA | |||