SLVSDR2 Data sheet

SLVSDR2C November 2018 – March 2025 ADC12DJ3200QML-SP

PRODUCTION DATA

5.9 Timing Requirements

			SUBGROUP⁽¹⁾	MIN	NOM	MAX	UNIT
DEVICE (Sampling) CLOCK (CLK+, CLK–)
f_CLK	Input clock frequency (CLK+, CLK–), both single-channel and dual-channel modes⁽²⁾	Maximum input clock frequency	[4, 5, 6]	3200			MHz
f_CLK		Minimum input clock frequency			800		MHz
SYSREF (SYSREF+, SYSREF–)
t_CLK	Input clock period (CLK+, CLK–), both single-channel and dual-channel modes⁽²⁾	Maximum input clock frequency	[4, 5, 6]	312.5			ps
t_CLK		Minimum input clock frequency			1250		ps
t_INV(SYSREF)	Duration of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by the SYSREF_POS status register⁽³⁾				48		ps
t_INV(TEMP)	Drift of invalid SYSREF capture region over temperature, a positive number indicates a shift toward the MSB of the SYSREF_POS register				0		ps/°C
t_INV(VA11)	Drift of invalid SYSREF capture region over the VA11 supply voltage, a positive number indicates a shift toward the MSB of the SYSREF_POS register				0.36		ps/mV
t_STEP(SP)	Delay of the SYSREF_POS LSB	SYSREF_ZOOM = 0			77		ps
t_STEP(SP)	Delay of the SYSREF_POS LSB	SYSREF_ZOOM = 1			24		ps
t_{(PH_SYS)}	Minimum SYSREF± assertion duration after a SYSREF± rising edge event				4		ns
t_{(PL_SYS)}	Minimum SYSREF± de-assertion duration after a SYSREF± falling edge event				4		ns
JESD204B SYNC TIMING ( SYNCSE OR TMSTP±)
t_H( SYNCSE)	Minimum hold time from multiframe boundary (SYSREF rising edge captured high) to de-assertion of JESD204B SYNC signal ( SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for NCO synchronization (NCO_SYNC_ILA = 1)	JMODE = 0, 2, 4, 6, 10, 13 or 15			21		t_CLK cycles
		JMODE = 1, 3, 5, 7, 9, 11, 14 or 16			17
		JMODE = 12, 17 or 18			9
t_SU( SYNCSE)	Minimum setup time from de-assertion of JESD204B SYNC signal ( SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) to multiframe boundary (SYSREF rising edge captured high) for NCO synchronization (NCO_SYNC_ILA = 1)	JMODE = 0, 2, 4, 6, 10, 13 or 15			–2		t_CLK cycles
		JMODE = 1, 3, 5, 7, 9, 11, 14 or 16			2
		JMODE = 12, 17 or 18			10
t_( SYNCSE)	SYNCSE minimum assertion time to trigger link resynchronization				4		Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
f_CLK(SCLK)	Serial clock frequency		[4, 5, 6]	0.0		15.625	MHz
t_(PH)	Serial clock high value pulse duration		[4, 5, 6]	32			ns
t_(PL)	Serial clock low value pulse duration		[4, 5, 6]	32			ns
t_SU( SCS)	Setup time from SCS to rising edge of SCLK		[4, 5, 6]	25			ns
t_H( SCS)	Hold time from rising edge of SCLK to SCS		[4, 5, 6]	3			ns
t_SU(SDI)	Setup time from SDI to rising edge of SCLK		[4, 5, 6]	25			ns
t_H(SDI)	Hold time from rising edge of SCLK to SDI		[4, 5, 6]	3			ns

(1) For subgroup definitions, please see Table 5-1.

(2) Unless functionally limited to a smaller range in Table 6-18 based on the programmed JMODE.

(3) Use SYSREF_POS to select an optimal SYSREF_SEL value for SYSREF capture, see SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) for more information on SYSREF windowing. The invalid region, specified by t_INV(SYSREF), indicates the portion of the CLK± period (t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.