SLVSE16E May   2019  – September 2026 TPS1HB08-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Thermal Shutdown
        2. 8.3.1.2 Current Limit
          1. 8.3.1.2.1 Current Limit Foldback
          2. 8.3.1.2.2 Programmable Current Limit
          3. 8.3.1.2.3 Undervoltage Lockout (UVLO)
          4. 8.3.1.2.4 VBB During Short-to-Ground
        3. 8.3.1.3 Voltage Transients
          1. 8.3.1.3.1 Load Dump
          2. 8.3.1.3.2 Driving Inductive Loads
        4. 8.3.1.4 Reverse Battery
        5. 8.3.1.5 Fault Event – Timing Diagrams - Version A and B
        6. 8.3.1.6 Fault Event – Timing Diagrams - Version F
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Switch Enabled
          2. 8.3.2.1.2 Detection With Switch Disabled
        2. 8.3.2.2 SNS Output
          1. 8.3.2.2.1 RSNS Value
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Fault Indication and SNS Mux
        4. 8.3.2.4 Resistor Sharing
        5. 8.3.2.5 High-Frequency, Low Duty-Cycle Current Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Off
      2. 8.4.2 Standby
      3. 8.4.3 Diagnostic
      4. 8.4.4 Standby Delay
      5. 8.4.5 Active
      6. 8.4.6 Fault
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Ground Protection Network
      2. 9.1.2 Interface With Microcontroller
      3. 9.1.3 I/O Protection
      4. 9.1.4 Inverse Current
      5. 9.1.5 Loss of GND
      6. 9.1.6 Automotive Standards
        1. 9.1.6.1 ISO7637-2
        2. 9.1.6.2 TPS1HB08-Q1 AEC-Q100-012 Short-Circuit Reliability
      7. 9.1.7 Interference on Device Pins
      8. 9.1.8 Thermal Information
    2. 9.2 Typical Application: Resistive Heater Loads
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 RILIM Calculation
        3. 9.2.2.3 Diagnostics
          1. 9.2.2.3.1 Selecting the RISNS Value
    3. 9.3 Typical Application: Headlight Bulb Loads
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.1.6.1 ISO7637-2

The TPS1HB08-Q1 is tested according to the ISO7637-2:2011 (E) standard. The test pulses are applied both with the switch enabled and disabled. The test setup includes only the DUT and minimal external components: CVBB, COUT, DGND, and RGND.

Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as: “The function does not perform as designed during the test but returns automatically to normal operation after the test”. See Table 9-2 for ISO7637-2:2011 (E) expected results.

Table 9-2 ISO7637-2:2011 (E) Results
TEST PULSETEST PULSE SEVERITY LEVEL WITH STATUS II FUNCTIONAL PERFORMANCEMINIMUM NUMBER OF PULSES OR TEST TIMEBURST CYCLE / PULSE REPETITION TIME
LEVELUSMINIMUMMAXIMUM
1III–112V500 pulses0.5s—
2a(1)III+55V500 pulses0.205s
2bIV+10V10 pulses0.5s5s
3aIV–220V1 hour90ms100ms
3bIV+150V1 hour90ms100ms
(1) 1µF capacitance on CVBB is required for passing level 3 ISO7637 pulse 2A.