SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.7 Current Limit

The internal current limit, ILIM, is the current limit value. There are two types of current limit behavior, depending on the value of the CLM pin. First, when CLM is high, there is brick-wall current limit. When CLM is low, there is turn-off current limit. CLM may be connected directly to VIN or directly to GND to control the current limit operation. Do not change the value of this pin when the device is enabled, and do not float this pin.

Brick-wall current limit, also known as constant current limit, is shown in Figure 8-5. In this mode, once ILIM is reached and the current limit circuitry has time to respond, the TPS7H1111 LDO will enter constant current regulation mode. In other words, the output voltage will drop to whatever value is needed to keep the output current at ILIM. Once the fault is removed the device will resume regulation. Generally, there will be the same soft start time as during initial startup since the SS_SET pin is pulled-low to quickly discharge the CSS capacitor during a fault. However, if the fault is extremely quick, the CSS capacitor may not be fully discharged which would result in a quicker startup time.

Due to the high power dissipation in brick-wall current limit, there is the possibility that the TPS7H1111 will enter thermal shutdown which causes the device to stop regulation until it cools enough to exit thermal shutdown.

WARNING: The TPS7H1111 is not intended to indefinitely remain in brick-wall current limit mode.
GUID-20210115-CA0I-VQZD-FV8Z-WKXMDQZRTZC9-low.svg Figure 8-5 Simplified Brick-Wall Current Limit Waveforms (CLM High)

Alternatively, if CLM is low, there is turn-off current limit. The behavior is shown in Figure 8-6. In turn-off current limit, if current limit, ILIM, is reached, the TPS7H1111 LDO will stop regulating (after a brief delay ~28 µs). The LDO will not resume regulation until EN is cycled (brought low then brought high).

The primary advantage of turn-off current limit is that there is no sustained high power dissipation after current limit is reached. However, the main disadvantage is that the device will not automatically resume regulation once the fault is removed. Therefore, an external monitor must determine when a fault has occurred and decide when to toggle the EN pin. This can normally be easily implemented by an existing device (such as an FPGA or microcontroller) monitoring the PG pin. If the monitor detects the PG pin deassert, it can then toggle EN to attempt to resume regulation.

When EN is being toggled from high to low to high, it must be low for at least tEN_LOW (20 µs). Additionally, it is recommended to not toggle EN until SS_SET has discharged to 5% of its nominal value in order to have sufficient soft-start during restart to avoid immediately reentering current limit.

GUID-20210115-CA0I-9XBB-QMFG-38357C7STJJ7-low.svg Figure 8-6 Simplified Turn-Off Current Limit Waveforms (CLM Low)