SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Options Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Typical Characteristics

VIN = 2.5 V, VOUT = 1.8 V, VBIAS = 5 V, IOUT = 1 A, COUT = 2 × 100 µF, CSS = 4.7 µF, RREF = 12.0 kΩ, RBIAS = 10 Ω, CBIAS = 4.7 µF, TA = 25°C, unless otherwise noted, integrated noise reported with 10-Hz to 100-kHz bandwidth.

GUID-20211210-SS0I-RXCV-ZHQR-D5WHWPP9ZK83-low.svg
VBIAS = 5 V
Figure 6-1 PSRR vs Frequency (Common Configurations)
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VIN = VOUT + VDO VOUT = 1.8 V VBIAS = VOUT + 1.6 V
Figure 6-3 PSRR vs Frequency Across Dropout
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VIN = VOUT + 0.8 V VBIAS = VIN + 1.6 V
Figure 6-5 PSRR vs Frequency Across Output Voltage
GUID-20220808-SS0I-9W62-LWMR-LPD7JBC37FMX-low.svg
See Table 9-4 for capacitor part numbers utilized.
Figure 6-7 PSRR vs Frequency Across Output Capacitors
GUID-20211210-SS0I-WNLF-BQFF-4KWBZKRDBSLJ-low.svgFigure 6-9 PSRR vs Frequency Across Bias Supply
GUID-20221208-SS0I-HGPT-RJTF-TQTBXDDGFJBN-low.svg
RBIAS = 0 Ω CBIAS = 0 µF
Figure 6-11 PSRR vs Frequency With VIN = VBIAS
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RBIAS = 10 Ω
Figure 6-13 PSRRBIAS vs Frequency Across Bias Voltage With RC
GUID-20211210-SS0I-LMZQ-SW91-9KF5SRZPPJ4P-low.svgFigure 6-15 Output Noise vs Frequency Across CSS (Noise Spectral Density)
GUID-20220808-SS0I-MLWF-5CMJ-SBQK1VPLQHCG-low.svg
See Table 9-4 for capacitor part numbers utilized.
Figure 6-17 Output Noise vs Frequency Across Output Capacitor (Noise Spectral Density)
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VOUT = VIN – 0.8 V
Figure 6-19 Output Noise vs Frequency Across Input Voltage (Noise Spectral Density)
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VBIAS = 12 V
Figure 6-2 PSRR vs Frequency (Common Configurations)
GUID-20211210-SS0I-X2HL-B5P8-8SLZGQNC0PVS-low.svgFigure 6-4 PSRR vs Frequency Across Output Current
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VOUT = VIN – 0.8 V VBIAS = VOUT + 1.6 V
Figure 6-6 PSRR vs Frequency Across Input Voltage
GUID-20211210-SS0I-XKBD-BXR7-FHV6MFH1L5HZ-low.svgFigure 6-8 PSRR vs Frequency Across Soft Start Capacitance
GUID-20211210-SS0I-DXVJ-N3W6-JXCBV4FVDDRL-low.svg
IOUT = 500 mA
Figure 6-10 PSRR vs Frequency Across Temperature
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RBIAS = 0 Ω
Figure 6-12 PSRRBIAS vs Frequency Across Bias Voltage Without RC
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IOUT = 500 mA
Figure 6-14 PSRRBIAS vs Frequency Across Temperature
GUID-20211210-SS0I-W5N9-NCGS-64TFVTSZKNFB-low.svgFigure 6-16 Output Noise vs Frequency Across Output Current (Noise Spectral Density)
GUID-20220808-SS0I-7SLG-HWH0-QNKR5TNZ240F-low.svg
VIN = VOUT + 0.8 V
Figure 6-18 Output Noise vs Frequency Across Output Voltage (Noise Spectral Density)
GUID-20220809-SS0I-RH9B-RD05-VW1W6XWFL91T-low.svg
COUT = 2 × 100 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
IOUT = 0 A: Phase Margin = 83°, Gain Margin = 29 dB
IOUT = 1.5 A: Phase Margin = 99°, Gain Margin = 19 dB
Figure 6-20 Gain and Phase vs Frequency (Bode Plot)
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COUT = 2 × 100 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
IOUT = 0 A: Phase Margin = 61°, Gain Margin = 27 dB
IOUT = 1.5 A: Phase Margin = 99°, Gain Margin = 12 dB
Figure 6-22 Gain and Phase vs Frequency (Bode Plot)
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COUT = 1 × 220 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
IOUT = 0 A: Phase Margin = 71°, Gain Margin = 30 dB
IOUT = 1.5 A: Phase Margin = 91°, Gain Margin = 14 dB
Figure 6-24 Gain and Phase vs Frequency (Bode Plot)
GUID-20220809-SS0I-3N7W-HTSB-BSJ7LKF5MLHX-low.svg
COUT = 1 × 220 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
IOUT = 0 A: Phase Margin = 72°, Gain Margin = 19 dB
IOUT = 1.5 A: Phase Margin = 66°, Gain Margin = 8 dB
Figure 6-26 Gain and Phase vs Frequency (Bode Plot)
GUID-20230111-SS0I-ZGQK-8RGF-JZJPM1WKZXJW-low.svg
Figure 6-28 Dropout Voltage vs Temperature
GUID-20230111-SS0I-48HD-BC4L-G7WC0FKDG1BZ-low.svgFigure 6-30 Dropout Voltage vs Temperature Without Separate VBIAS
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IOUT = 0 A
Figure 6-32 Quiescent Current vs Temperature
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IOUT = 1.5 A
Figure 6-34 Ground Current vs Temperature
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VEN = 0 V
Figure 6-36 Shutdown Current vs Temperature
GUID-20230120-SS0I-BBG8-VLM5-91LQHWC93MZF-low.svgFigure 6-38 SET Pin Current vs Temperature
GUID-20230105-SS0I-DWNC-LMTQ-H6ZLGZHLPMVL-low.svgFigure 6-40 Offset Voltage vs Current
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VEN = 7 V VIN = 7 V VBIAS = 14 V
Figure 6-42 Enable Leakage Current vs Temperature
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VIN = 0.85 V VBIAS = 2.2 V IOUT = 1 mA
IPG = 2 mA
Figure 6-44 PG Pin Output Low vs Temperature
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IOUT = 0 mA
Figure 6-46 SS_SET Pin Current During Startup vs Temperature
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0.85 V ≤ VIN ≤ 7 V, 2.2 V ≤ VBIAS ≤ 14 V, IOUT = 1 mA
Figure 6-48 Output Offset Voltage Distribution at TA = 25°C
GUID-20230103-SS0I-SVSQ-GN8X-DL7VPRGRCMJ7-low.svg
0.85 V ≤ VIN ≤ 7 V, 2.2 V ≤ VBIAS ≤ 14 V, IOUT = 1 mA
Figure 6-50 ISET Current Distribution at TA = –55°C
GUID-20230103-SS0I-XXTR-2SRR-NSCSZHNRWKQK-low.svg
0.85 V ≤ VIN ≤ 7 V, 2.2 V ≤ VBIAS ≤ 14 V, IOUT = 1 mA
Figure 6-52 ISET Current Distribution at TA = 125°C
GUID-20230103-SS0I-LTS6-MFJ9-GL3VRMXK0JRT-low.svg
0.85 V ≤ VIN ≤ 7 V, 1 mA ≤ IOUT ≤ 1.5 A, 2.2 V ≤ VBIAS ≤ 14 V, PD ≤ 4 W
Figure 6-54 Output Voltage Accuracy Distribution at TA = 25°C
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Slew Rate = 10.1 A/µs
Figure 6-56 Load Step: 1 mA to 1.5 A
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Slew Rate = 0.9 A/µs
Figure 6-58 Load Step: 1 mA to 1.5 A
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Slew Rate = 8.5 A/µs IOUT is only the stepped current, parallel 0.5 A load not shown
Figure 6-60 Load Step: 0.5 A to 1.5 A
GUID-20230124-SS0I-HXDB-LNG8-KM75JXJFMBJ4-low.svg
Slew Rate = 20.2 V/ms VOUT = 0.4 V
Figure 6-62 Line Step: 1.8 V to 5 V With IOUT = 1.5 A
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Slew Rate = 84.0 V/ms VOUT = 0.4 V
Figure 6-64 Line Step: 1.8 V to 5 V With IOUT = 1 mA
GUID-20230111-SS0I-PB3P-K2TX-QMHNHP577MZW-low.svgFigure 6-66 Startup Waveform
GUID-20221202-SS0I-WJ8N-ZHTJ-RCS1VXCXPL5X-low.svg
COUT = 2 × 100 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 98°, Gain Margin = 19 dB
Figure 6-21 Gain and Phase vs Frequency (Bode Plot)
GUID-20221202-SS0I-GZC9-G9FQ-T0TBXKBHD8MB-low.svg
COUT = 2 × 100 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 98°, Gain Margin = 13 dB
Figure 6-23 Gain and Phase vs Frequency (Bode Plot)
GUID-20221202-SS0I-RLMX-N8VX-SQMX9LDSRN1H-low.svg
COUT = 1 × 220 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 98°, Gain Margin = 14 dB
Figure 6-25 Gain and Phase vs Frequency (Bode Plot)
GUID-20221202-SS0I-DK4X-DDJJ-Z5CN8DPSSSMN-low.svg
COUT = 1 × 220 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 94°, Gain Margin = 9 dB
Figure 6-27 Gain and Phase vs Frequency (Bode Plot)
GUID-20230202-SS0I-GHQV-F7RL-WVPMKPCFFRPP-low.svg
VIN = 5 V VBIAS = VIN + 1.6 V
Figure 6-29 Dropout Voltage vs Current
GUID-20230202-SS0I-RZDC-4DMZ-9S8JVJQQVXJB-low.svg
Figure 6-31 Dropout Voltage vs Current Without Separate VBIAS
GUID-20230111-SS0I-RZSD-QXWW-T4KZGKFB2B5C-low.svg
IOUT = 0 A
Figure 6-33 Bias Current vs Temperature
GUID-20230111-SS0I-NLF1-0R4W-NRGQ1W392Q1C-low.svg
IOUT = 1.5 A
Figure 6-35 Bias Current vs Temperature
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VEN = 0 V
Figure 6-37 Bias Shutdown Current vs Temperature
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IOUT = 1 mA
Figure 6-39 Offset Voltage vs Temperature
GUID-20230105-SS0I-JCQX-PZKK-Q5RFFWTC8LKG-low.svgFigure 6-41 Output Voltage vs Temperature
GUID-20230120-SS0I-QJV3-8V0C-SGZ5FPCCNQPH-low.svg
VFB_PG = 6 V VIN = 7 V VBIAS = 14 V
IOUT = 1 mA
Figure 6-43 FB_PG Pin Leakage Current vs Temperature
GUID-20230120-SS0I-9PQZ-LBR5-GMXVHZTN56HP-low.svg
VIN = 7 V VBIAS = 14 V IOUT = 1 mA
VPG = 7 V
Figure 6-45 PG Pin Leakage vs Temperature
GUID-20221220-SS0I-6RRS-1SSM-SXBWLPLCDFBP-low.svg
0.85 V ≤ VIN ≤ 7 V, 2.2 V ≤ VBIAS ≤ 14 V, IOUT = 1 mA
Figure 6-47 Output Offset Voltage Distribution at TA = –55°C
GUID-20221220-SS0I-N3C7-4ZRG-ZZDHNFJND2T0-low.svg
0.85 V ≤ VIN ≤ 7 V, 2.2 V ≤ VBIAS ≤ 14 V, IOUT = 1 mA
Figure 6-49 Output Offset Voltage Distribution at TA = 125°C
GUID-20230103-SS0I-1H93-RGGZ-J5T5MVG5J8KX-low.svg
0.85 V ≤ VIN ≤ 7 V, 2.2 V ≤ VBIAS ≤ 14 V, IOUT = 1 mA
Figure 6-51 ISET Current Distribution at TA = 25°C
GUID-20230103-SS0I-G2PF-HS0N-4FGWBCFKRZHC-low.svg
0.85 V ≤ VIN ≤ 7 V, 1 mA ≤ IOUT ≤ 1.5 A, 2.2 V ≤ VBIAS ≤ 14 V, PD ≤ 4 W
Figure 6-53 Output Voltage Accuracy Distribution at TA = –55°C
GUID-20230103-SS0I-G6Z8-V6QM-7RTZ3N2M8VFG-low.svg
0.85 V ≤ VIN ≤ 7 V, 1 mA ≤ IOUT ≤ 1.5 A, 2.2 V ≤ VBIAS ≤ 14 V, PD ≤ 4 W
Figure 6-55 Output Voltage Accuracy Distribution at TA = 125°C
GUID-20230124-SS0I-7F3B-1C37-9PMZKFSLL8T6-low.svg
Slew Rate = 13.1 A/µs
Figure 6-57 Load Step: 1.5 A to 1 mA
GUID-20230105-SS0I-SQ4R-Z4WX-J1LGS1CF1KB5-low.svg
Slew Rate = 1.0 A/µs
Figure 6-59 Load Step: 1.5 A to 1 mA
GUID-20230124-SS0I-FQS7-BNRV-KJSSNBNV4LQ2-low.svg
Slew Rate = 8.1 A/µs IOUT is only the stepped current, parallel 0.5 A load not shown
Figure 6-61 Load Step: 1.5 A to 0.5 A
GUID-20230124-SS0I-TTDL-RV7D-MBLRQN0GRGZD-low.svg
Slew Rate = 144.8 V/ms VOUT = 0.4 V
Figure 6-63 Line Step: 5 V to 1.8 V With IOUT = 1.5 A
GUID-20230124-SS0I-0J4J-JDP6-FRGKN9B3SJHD-low.svg
Slew Rate = 85.1 V/ms VOUT = 0.4 V
Figure 6-65 Line Step: 5 V to 1.8 V With IOUT = 1 mA