SLVSFY0A August   2021  – May 2026 TPS51488

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2 Advanced Eco-mode Control
      3. 6.3.3 Soft Start and Prebiased Soft Start
      4. 6.3.4 Power Good
      5. 6.3.5 Overcurrent Protection and Undervoltage Protection
      6. 6.3.6 Overvoltage Protection
      7. 6.3.7 UVLO Protection
      8. 6.3.8 Output Voltage Discharge
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Light Load Operation for VDD1 Buck and VDD2 Buck
      2. 6.4.2 Output State Control
      3. 6.4.3 Output Sequence Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Selection
          1. 7.2.2.1.1 Inductor Selection
          2. 7.2.2.1.2 Output Capacitor Selection
          3. 7.2.2.1.3 Input Capacitor Selection
          4. 7.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1 Application Information

The TPS51488 device provides a complete power design for a LPDDR5 memory system. Table 7-1 shows the power requirements for LPDDR5.

Table 7-1 LPDDR5 Application
VDD1VDD2VDDQ
LPDDR5YESYESYES

Figure 7-1 shows a typical application for LPDDR5. For VDD2 buck, the PVIN supports a 4.5-V to 24-V input range with 1.065-V VDD2 output, and the continuous current capability is 8 A. Usually, the PVIN_VDD1 and VCC_5V can share one 5-V power input and support 1.8-V VDD1 output with 1-A continuous current capability. The PVIN_VDD1 can be lowered down to a 3.3-V power supply. The VLDOIN power input usually is connected to the VDD2 output. The VLDOIN power input can also be connected to external power supply input.