SLVSFY0A August   2021  – May 2026 TPS51488

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2 Advanced Eco-mode Control
      3. 6.3.3 Soft Start and Prebiased Soft Start
      4. 6.3.4 Power Good
      5. 6.3.5 Overcurrent Protection and Undervoltage Protection
      6. 6.3.6 Overvoltage Protection
      7. 6.3.7 UVLO Protection
      8. 6.3.8 Output Voltage Discharge
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Light Load Operation for VDD1 Buck and VDD2 Buck
      2. 6.4.2 Output State Control
      3. 6.4.3 Output Sequence Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Selection
          1. 7.2.2.1.1 Inductor Selection
          2. 7.2.2.1.2 Output Capacitor Selection
          3. 7.2.2.1.3 Input Capacitor Selection
          4. 7.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.2 Advanced Eco-mode Control

The VDD1 buck and VDD2 buck are designed with advanced Eco-mode control schemes to maintain high light load efficiency. As the output current decreases from heavy load conditions, the inductor current is also reduced and eventually comes to a point where the rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The on time is kept almost the same as the on time is in continuous conduction mode, so that discharging the output capacitor with smaller load current to the level of the reference voltage takes longer time. This makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The light load current where the transition to Eco-mode operation happens (IOUT(LL)) can be calculated from Equation 2.

Equation 2. TPS51488

After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). Sizing the inductor properly so that the valley current does not hit the negative low-side current limit is important.