SLVSFY0A August   2021  – May 2026 TPS51488

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2 Advanced Eco-mode Control
      3. 6.3.3 Soft Start and Prebiased Soft Start
      4. 6.3.4 Power Good
      5. 6.3.5 Overcurrent Protection and Undervoltage Protection
      6. 6.3.6 Overvoltage Protection
      7. 6.3.7 UVLO Protection
      8. 6.3.8 Output Voltage Discharge
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Light Load Operation for VDD1 Buck and VDD2 Buck
      2. 6.4.2 Output State Control
      3. 6.4.3 Output Sequence Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Selection
          1. 7.2.2.1.1 Inductor Selection
          2. 7.2.2.1.2 Output Capacitor Selection
          3. 7.2.2.1.3 Input Capacitor Selection
          4. 7.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to 125°C, VPVIN= 12 V, VPVIN_VDD1 = 5 V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY VOLTAGE
IVCC_5VVCC_5V supply currentVVDD_EN = VVDDQ_EN = 0 V5µA
VVDD_EN = 5 V, VVDDQ_EN = 0 V, no load110µA
VVDD_EN = VVDDQ_EN = 5 V, no load150µA
VINPVIN input voltage range4.524V
UVLO
UVLOVCC_5V undervoltage lockoutWake up VCC_5V voltage4.14.5V
Shut down VCC_5V voltage3.33.6V
Hysteresis VCC_5V voltage500mV
VDD2
VVDD2SNSVDD2 sense voltage1.0541.0651.076V
IVDD2SNSVDD2SNS input currentVVDD2SNS =1.065 V35µA
IVDD2DISVDD2 discharge currentVVDD_EN = VVDDQ_EN = 0 V, VVDD2SNS = 0.5 V12mA
tVDD2SSVDD2 soft-start time1.62.65ms
tVDD2DLYVDD2 ramp up delay time2ms
RDSONHHigh-side switch resistanceTJ = 25°C, VPVIN = 19 V, VVCC_5V = 5 V22mΩ
RDSONLLow-side switch resistanceTJ = 25°C, VPVIN = 19 V, VVCC_5V = 5 V8.6mΩ
IVDD2OCLLow-side valley current limitedVOUT = 1.065 V, L = 0.68 µH, TJ = –40°C to 125°C8.29.811.5A
VOUT = 1.065 V, L = 0.68 µH, TJ = 0°C to 125°C8.69.811.5A
fswVDD2 switching frequency600kHz
tOFF(MIN)Minimum off time198ns
PGOOD (VDD2, VDD1)
VTHPGPGOOD thresholdVDD2SNS / VDD1SNS falling (fault)87%
VDD2SNS / VDD1SNS rising (good)93%
VDD2SNS / VDD1SNS rising (fault)115%
VDD2SNS / VDD1SNS falling (Good)110%
IPGMAXPG sink currentVPGOOD = 0.5 V, VVDD_EN = VVDDQ_EN = 5 V, no load46mA
tPGDLYPG start-up delayPG from low to high1ms
VDD1
VVDD1SNSVDD1 sense voltage1.751.81.85V
IVDD1SNSVDD1SNS input currentVVDD1SNS = 1.8 V20µA
IVDD1DISVDD1 discharge currentVVDD_EN = VVDDQ_EN = 0 V, VVDD1SNS = 0.5 V12mA
tVDD1SSVDD1 soft-start time1.02ms
RDSONHHigh-side switch resistanceTJ = 25°C, VPVIN_VDD1 = 5 V, VVCC_5V = 5 V150mΩ
RDSONLLow-side switch resistanceTJ = 25°C, VPVIN_VDD1 = 5 V, VVCC_5V = 5 V120mΩ
IVDD1OCLLow-side valley current limitedVVDD1SNS = 1.8 V, L = 4.7 µH1.522.5A
fswVDD1 switching frequency580kHz
tOFF(MIN)Minimum off time195ns
OVP AND UVP (VDD2, VDD1)
VOVPOVP threshold voltageOVP detect voltage120%125%130%
VUVP1UVP threshold voltageUVP detect voltage57.5%62.5%67.5%
tOVPDLYOVP delay20µs
tUVPDLYUVP delay250µs
VDDQ OUTPUT
VVDDQOutput voltageTJ = 25°C, IVDDQ ≤ 1.5 A0.4750.50.525V
IVDDQOCLSRCSource current limitVVDD2SNS = 1.065 V, VVDDQ = VVDDQSNS= 0.4 V

1.55

2.2A
IVDDQLKLeakage currentTJ = 25°C, VVDD_EN = 5 V, VVDDQ_EN = 5 V5µA
IVDDQSNSBIASVDDQSNS input bias currentVVDD_EN = 5 V, VVDDQ_EN = 5 V–0.500.5
IVDDQSNSLKVDDQSNS leakage currentVVDD_EN = 5 V, VVDDQ_EN = 0 V–101
IVDDQDLYVDDQ output delay relative to VDDQ_EN35μs
IVDDQDISVDDQ discharge currentTJ = 25°C, VVDD_EN = VVDDQ_EN = 0 V, VVDD2SNS = 1.065 V, VVDDQ = 0.4 V5.7mA
VDD_EN, VDDQ_EN LOGIC THRESHOLD
VIHVDD_EN/VDDQ_EN high-level voltage1.35V
VILVDD_EN/VDDQ_EN low-level voltage0.5V
RTOGNDVDD_EN/VDDQ_EN resistance to GND500kΩ
THERMAL PROTECTION
TOTPOTP trip threshold150°C
TOTPHSYOTP hysteresis20°C