SLVSGL6B July   2022  – October 2026 TPS1HC30-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SNS Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Accurate Current Sense
      2. 7.3.2 Programmable Current Limit
        1. 7.3.2.1 Current Limit Accuracy Across VDS
        2. 7.3.2.2 Capacitive Charging
      3. 7.3.3 Inductive-Load Switching-Off Clamp
      4. 7.3.4 Full Protections and Diagnostics
        1. 7.3.4.1  Short-Circuit and Overload Protection
        2. 7.3.4.2  Open-Load and Short-to-Battery Detection
        3. 7.3.4.3  Short-to-Battery Detection
        4. 7.3.4.4  Reverse-Polarity and Battery Protection
        5. 7.3.4.5  Latch-Off Mode
        6. 7.3.4.6  Thermal Protection Behavior
        7. 7.3.4.7  UVLO Protection
        8. 7.3.4.8  Loss of GND Protection
        9. 7.3.4.9  Loss of Power Supply Protection
        10. 7.3.4.10 Reverse Current Protection
        11. 7.3.4.11 Protection for MCU I/Os
      5. 7.3.5 Diagnostic Enable Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Dynamically Changing Current Limit
        2. 8.2.2.2 EMC Transient Disturbances Test
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Without a GND Network
        2. 8.4.2.2 With a GND Network
      3. 8.4.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.2 EMC Transient Disturbances Test

Due to the severe electrical conditions in the automotive environment, immunity capacity against electrical transient disturbances is required, especially for a high side power switch, which connects directly to the battery. Detailed test requirements are in accordance with the ISO 7637-2:2011 and ISO 16750-2:2010 standards. The TPS1HC30-Q1 device is tested and certificated by a third-party organization.

Table 8-2 ISO 7637-2:2011(E) in 12V System(1)(2)(3)(4)
TEST ITEMTEST PULSE SEVERITY LEVEL AND VS ACCORDINGLYPULSE DURATION (td)MINIMUM NUMBER OF PULSES OR TEST TIMEBURST-CYCLE PULSE-REPETITION TIMEINPUT RESISTANCE (Ω)FUNCTION PERFORMANCE STATUS CLASSIFICATION
LEVELVs/VMINMAX
1III–1122ms500 pulses0.5s—10Status II
2aIII5550µs500 pulses0.2s5s2Status II
2bIV100.2 to 2s10 pulses0.5s5s0 to 0.05Status II
3aIV–2200.1µs1h90ms100ms50Status II
3bIV1500.1µs1h90ms100ms50Status II
(1) Tested both under input low condition and high condition.
(2) The pulse 2A voltage is 54V maximum from VBB with respect to ground. A voltage suppressing mechanism must be used to pass Level III. This test runs with an 2μF capacitor from VBB to ground.
(3) GND pin network is a 1kΩ resistor in parallel with a diode BAS21-7F.
(4) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.
Table 8-3 ISO 16750-2:2010(E) Load Dump Test B in 12V System(1)(2)(3)(4)(5)
TEST ITEMTEST PULSE SEVERITY LEVEL AND VS ACCORDINGLYPULSE DURATION (td)MINIMUM NUMBER OF PULSES OR TEST TIMEBURST-CYCLE PULSE-REPETITION TIMEINPUT RESISTANCE (Ω)FUNCTION PERFORMANCE STATUS CLASSIFICATION
LEVEL Vs/V
Test B3540 to 400ms5 pulses60s0.5 to 4Status II
(1) Tested both under input low condition and high condition (DIAG_EN, EN, and VBB are all classified as inputs).
(2) Considering the worst test condition, the device is tested without any filter capacitors on VBB and VOUT.
(3) The GND pin network is a 1kΩ resistor in parallel with a diode BAS21-7F.
(4) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.
(5) Select a 36V external suppressor.