SLVSGM1C July   2023  – April 2025 TPSM828301 , TPSM828302 , TPSM828303

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RDS Package
    5. 6.5 Thermal Information VCB Package
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse Width Modulation (PWM) Operation
      2. 7.3.2 Power Save Mode (PSM) Operation
      3. 7.3.3 Start-Up and Soft Start
      4. 7.3.4 Switch Cycle-by-Cycle Current Limit
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Optimized EMI Performance
      8. 7.3.8 VOUT Accuracy
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Disable, and Output Discharge
      2. 7.4.2 Minimum Duty Cycle and 100% Mode Operation
      3. 7.4.3 Power Good
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

7.3.8 VOUT Accuracy

The output voltage accuracy of TPSM82830x depends on various contributors listed in Table 7-1. Mitigation possibilities and responsibility are listed to help selecting correct design measures for the application.

Table 7-1 Output Voltage Accuracy
CONTRIBUTOR MITIGATION RESPONSIBILITY
Feedback divider Higher resistor accuracy of feedback divider Circuit designer
Error amplifier Device calibration Device manufacturer
Reference voltage Device calibration Device manufacturer
Input voltage and input voltage transients Low impedance power source, input capacitor adapted to load step Circuit designer
Load current and load current transients Output capacitor adapted to load step Circuit designer
Noise Input filter, on die filter, pinout, layout Circuit designer and device manufacturer
Board layout Separate noisy signals from noise sensitive signals, control slew rate on digital signals located close to sensitive signals Circuit designer and device manufacturer

Output transients can have significant impact on VOUT accuracy. Slow changes can be compensated by the regulation loop and do not require attendance. Fast transient like those in system on chips or microprocessors can exceed the speed of the regulation loop and require output capacitance as temporary energy reservoir. The DCS topology allows reducing the output capacitance for changes occurring over multiple switching cycles. When the load step is instant, which means the complete load step happens within one clock cycles, then sufficient output capacitance is needed. This need is supported by the TPSM82830x with large output capacitance tolerance.

The PG pin of TPSM82830x is located near the sensitive VOS pin on the die. Therefore, some impact of PG toggling on the output voltage can be seen (see PG to VOUT Influence). The effect can be minimized by keeping VOS and FB in the layout as far apart from PG as possible. If the layout is very dense then the effect can also be minimized by adding a capacitor of up to 33nF to the PG pin. As a mitigation measure, the circuit designer can add the footprint for an optional capacitor connected to PG in the layout.