SLVSH61D March   2025  – September 2026 TPS7H4102-SEP , TPS7H4104-SEP , TPS7H4104-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2 Voltage Reference
      3. 8.3.3 Setting VOUTx
        1. 8.3.3.1 VOUTx with Error
        2. 8.3.3.2 Minimum Output Voltage
        3. 8.3.3.3 Maximum Output Voltage
      4. 8.3.4 Enable and EN_SEQ
        1. 8.3.4.1 ENx and External UVLO
        2. 8.3.4.2 Sequence UP/DOWN (EN_SEQ)
      5. 8.3.5 Power Good (PWRGDx)
      6. 8.3.6 Adjustable Switching Frequency, Synchronization (SYNC) and Relative Phase Shift
        1. 8.3.6.1 Internal Clock Mode
        2. 8.3.6.2 External Clock Mode and Switchover
        3. 8.3.6.3 Relative Phase Shift
      7. 8.3.7 Turn-On Behavior
        1. 8.3.7.1 Pulse Skipping During Start-up
        2. 8.3.7.2 Soft-Start (SS_TRx)
        3. 8.3.7.3 Safe Start-up Into Pre-biased Outputs
        4. 8.3.7.4 Tracking and Sequencing (SS_TRx)
      8. 8.3.8 Protection Modes
        1. 8.3.8.1 Overcurrent Protection
          1. 8.3.8.1.1 High-Side Cycle by Cycle Overcurrent Protection (IOC_HSx)
          2. 8.3.8.1.2 Low-Side Sourcing Overcurrent Protection (IOC_LS_SOURCINGx)
          3. 8.3.8.1.3 COMPx Clamp Shutdown (COMPxCLAMP)
          4. 8.3.8.1.4 Low-Side Overcurrent Sourcing and Sinking Protection
        2. 8.3.8.2 Output Overvoltage Protection (OVP)
        3. 8.3.8.3 Thermal Shutdown
      9. 8.3.9 Error Amplifier and Loop Response
        1. 8.3.9.1 Error Amplifier
        2. 8.3.9.2 Power Stage Transconductance
        3. 8.3.9.3 Slope Compensation
        4. 8.3.9.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
        8. 9.2.2.8 Slope Compensation Requirements
        9. 9.2.2.9 Compensation Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 Parallel Operation
      1. 9.3.1 Input and Output Capacitance Reduction
        1. 9.3.1.1 Output Capacitance Reduction
        2. 9.3.1.2 Input Capacitance Reduction
    4. 9.4 Termination Guidelines for Unused Channels
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.1 VIN and Power VIN Pins (VIN and PVIN)

The VIN pin provides power to internal control circuitry. The PVIN pins provide the input voltage (and power to the loads) to all the internal half-bridges (CH # 1 to CH # 4). Both pins have an input voltage range from 3V to 7V. The pins must be at the same nominal voltage and the pins must power-up and power-down at the same time. Generally this is achieved by providing the pins from the same voltage source (tied together).

Both VIN and PVIN have individual UVLO (under voltage lockout) rising thresholds, VUVLOR_VIN (2.7V typical) and VUVLOR_PVIN (2.44V typical), respectively. This is to make sure the device internal bias is sufficient for proper operation. Additionally, VIN and PVIN have individual UVLO falling thresholds, VUVLOF_VIN (2V typical) and VUVLOF_PVIN (2.52V typical), respectively. If the voltage falls and these values are reached, the device turns off. As PVIN and VIN are tied together in the application, the dominant UVLO for the device (or I.C.) is the VIN UVLO as is the higher threshold value during a rising and falling voltage.

If desired, the user can adjust the effective UVLO by using an external resistive voltage divider, connected between VIN and ENx. For more details, see Section 8.3.4.1.

Note: In the TPS7H4102 the PVIN pins 17, 18, 31 and 32 do not conduct much current with a maximum of 2.27mA. For this reason the pins do not need to be connected to a plane, rather a trace is sufficient.