SLVSH61D March   2025  – September 2026 TPS7H4102-SEP , TPS7H4104-SEP , TPS7H4104-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2 Voltage Reference
      3. 8.3.3 Setting VOUTx
        1. 8.3.3.1 VOUTx with Error
        2. 8.3.3.2 Minimum Output Voltage
        3. 8.3.3.3 Maximum Output Voltage
      4. 8.3.4 Enable and EN_SEQ
        1. 8.3.4.1 ENx and External UVLO
        2. 8.3.4.2 Sequence UP/DOWN (EN_SEQ)
      5. 8.3.5 Power Good (PWRGDx)
      6. 8.3.6 Adjustable Switching Frequency, Synchronization (SYNC) and Relative Phase Shift
        1. 8.3.6.1 Internal Clock Mode
        2. 8.3.6.2 External Clock Mode and Switchover
        3. 8.3.6.3 Relative Phase Shift
      7. 8.3.7 Turn-On Behavior
        1. 8.3.7.1 Pulse Skipping During Start-up
        2. 8.3.7.2 Soft-Start (SS_TRx)
        3. 8.3.7.3 Safe Start-up Into Pre-biased Outputs
        4. 8.3.7.4 Tracking and Sequencing (SS_TRx)
      8. 8.3.8 Protection Modes
        1. 8.3.8.1 Overcurrent Protection
          1. 8.3.8.1.1 High-Side Cycle by Cycle Overcurrent Protection (IOC_HSx)
          2. 8.3.8.1.2 Low-Side Sourcing Overcurrent Protection (IOC_LS_SOURCINGx)
          3. 8.3.8.1.3 COMPx Clamp Shutdown (COMPxCLAMP)
          4. 8.3.8.1.4 Low-Side Overcurrent Sourcing and Sinking Protection
        2. 8.3.8.2 Output Overvoltage Protection (OVP)
        3. 8.3.8.3 Thermal Shutdown
      9. 8.3.9 Error Amplifier and Loop Response
        1. 8.3.9.1 Error Amplifier
        2. 8.3.9.2 Power Stage Transconductance
        3. 8.3.9.3 Slope Compensation
        4. 8.3.9.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
        8. 9.2.2.8 Slope Compensation Requirements
        9. 9.2.2.9 Compensation Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 Parallel Operation
      1. 9.3.1 Input and Output Capacitance Reduction
        1. 9.3.1.1 Output Capacitance Reduction
        2. 9.3.1.2 Input Capacitance Reduction
    4. 9.4 Termination Guidelines for Unused Channels
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.7.4 Tracking and Sequencing (SS_TRx)

In addition to the internal sequence up/down (using EN_SEQ), typical sequence-up methodologies as described below can be implemented using the SS_TRx, ENx, and PWRGDx pins.

Note: The sequencing methodologies described below offer upwards control, however the system configuration does not offer reverse sequence down, needed in many applications. For sequential up and reverse sequence down use the EN_SEQ input as described on the Sequence UP/DOWN (EN_SEQ) section. For a more comprehensive sequence control the designers can use the TPS7H3014, a 3V to 14V space-grade sequencer.

The sequential method is shown in Figure 8-11. In this case channel # 1 and #2 of TPS7H4104 are used. As with any methodology discussed here, the figure can be expanded to any CHx (or from another point of load converter), however for simplicity the figure shows only 2 channels (in this case CH1 and CH2). The PWRGD1 pin of the first channel is coupled to the EN2 pin of the second channel, which enables the second power supply after the primary supply reaches regulation (typically 94% during a rising VOUTx voltage) . If a further delay is desired between sequencing of the first and second channel an optional CPWRGD1 capacitor can be included on PWRGD1 as well. This causes an RC delay based on the value of the power good pull-up resistor and the capacitor used.

TPS7H4104-SP TPS7H4104-SEP TPS7H4102-SEP Sequential Start-Up Sequence Figure 8-11 Sequential Start-Up Sequence

Figure 8-12 shows the method implementing ratiometric sequencing by connecting the SS_TR1 and SS_TR2 pins of two channels together (in this case channels # 1 and 2). The regulator outputs (VOUT1 and VOUT2) ramp up and reach regulation at the same time.

TPS7H4104-SP TPS7H4104-SEP TPS7H4102-SEP Ratiometric Start-Up Sequence Figure 8-12 Ratiometric Start-Up Sequence

Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network of R1 and R2 (shown in Figure Ratiometric and Simultaneous Start-Up Sequence) to the output of the power supply that must be tracked or another voltage reference source. Using Equation 22 and Equation 23, calculate the tracking resistors to initiate the VOUT2 slightly before, after, or at the same time as VOUT1. Equation 24 is the voltage difference between VOUT1 and VOUT2.

To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 22 and Equation 23 for ΔV. Equation 24 results in a positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.

The ΔV variable is 0V for simultaneous sequencing. To minimize the effect of the inherent SS_TRx to VSNSx offset (SS_TRxSTART_UP = 22mV typical) in the soft-start circuit and the offset created by the pullup current source (ISS_TRx = 2.28μA typical) and tracking resistors, the SS_TRxSTART_UP and ISS_TRx are included as variables in the equations.

To provide proper operation of the device, the calculated R1 value from Equation 22 must be greater than the value calculated in Equation 25.

Equation 22. R 1 =   V O U T 2 +   ∆ V   V R E F x   ×   S S _ T R x S T A R T _ U P   I S S _ T R x
Equation 23. R 2 =   V R E F x ×   R 1   V O U T 2   +   ∆ V - V R E F x
Equation 24. ∆ V = V O U T 1 - V O U T 2
Equation 25. R 1 > 2800   × V O U T 1 - 180   × ∆ V
TPS7H4104-SP TPS7H4104-SEP TPS7H4102-SEP Ratiometric and Simultaneous Start-Up Sequence Figure 8-13 Ratiometric and Simultaneous Start-Up Sequence