SLVSH61D March   2025  – September 2026 TPS7H4102-SEP , TPS7H4104-SEP , TPS7H4104-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2 Voltage Reference
      3. 8.3.3 Setting VOUTx
        1. 8.3.3.1 VOUTx with Error
        2. 8.3.3.2 Minimum Output Voltage
        3. 8.3.3.3 Maximum Output Voltage
      4. 8.3.4 Enable and EN_SEQ
        1. 8.3.4.1 ENx and External UVLO
        2. 8.3.4.2 Sequence UP/DOWN (EN_SEQ)
      5. 8.3.5 Power Good (PWRGDx)
      6. 8.3.6 Adjustable Switching Frequency, Synchronization (SYNC) and Relative Phase Shift
        1. 8.3.6.1 Internal Clock Mode
        2. 8.3.6.2 External Clock Mode and Switchover
        3. 8.3.6.3 Relative Phase Shift
      7. 8.3.7 Turn-On Behavior
        1. 8.3.7.1 Pulse Skipping During Start-up
        2. 8.3.7.2 Soft-Start (SS_TRx)
        3. 8.3.7.3 Safe Start-up Into Pre-biased Outputs
        4. 8.3.7.4 Tracking and Sequencing (SS_TRx)
      8. 8.3.8 Protection Modes
        1. 8.3.8.1 Overcurrent Protection
          1. 8.3.8.1.1 High-Side Cycle by Cycle Overcurrent Protection (IOC_HSx)
          2. 8.3.8.1.2 Low-Side Sourcing Overcurrent Protection (IOC_LS_SOURCINGx)
          3. 8.3.8.1.3 COMPx Clamp Shutdown (COMPxCLAMP)
          4. 8.3.8.1.4 Low-Side Overcurrent Sourcing and Sinking Protection
        2. 8.3.8.2 Output Overvoltage Protection (OVP)
        3. 8.3.8.3 Thermal Shutdown
      9. 8.3.9 Error Amplifier and Loop Response
        1. 8.3.9.1 Error Amplifier
        2. 8.3.9.2 Power Stage Transconductance
        3. 8.3.9.3 Slope Compensation
        4. 8.3.9.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
        8. 9.2.2.8 Slope Compensation Requirements
        9. 9.2.2.9 Compensation Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 Parallel Operation
      1. 9.3.1 Input and Output Capacitance Reduction
        1. 9.3.1.1 Output Capacitance Reduction
        2. 9.3.1.2 Input Capacitance Reduction
    4. 9.4 Termination Guidelines for Unused Channels
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
8.3.8.1.4 Low-Side Overcurrent Sourcing and Sinking Protection

The low-side MOSFET can sink current from the load (such as during light load operation). In certain situations (such as a high current load being suddenly removed or VOUT being raised above the set point), the low-side sink current can become excessive. Therefore, low-side overcurrent sinking protection is provided. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are off until the start of the next cycle. When the low-side MOSFET turns off, the switch node voltage increases and forward biases the high-side MOSFET parallel body diode (the high-side MOSFET is still off at this stage).