7 LM51251A-Q1 Registers

Table 7-1 lists the memory-mapped registers for the LM51251A-Q1 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 LM51251A-Q1 Registers

Offset	Acronym	Register Name	Section
0h	VOUT	VOUT	Section 7.1
1h	CONFIGURATION_1	CONFIGURATION_1	Section 7.2
2h	CONFIGURATION_2	CONFIGURATION_2	Section 7.3
3h	CONFIGURATION_3	CONFIGURATION_3	Section 7.4
4h	OPERATION_STATE	OPERATION_STATE	Section 7.5
5h	STATUS_BYTE	STATUS_BYTE	Section 7.6
6h	CLEAR_FAULTS	CLEAR_FAULTS	Section 7.7

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 LM51251A-Q1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.1 VOUT Register (Offset = 0h) [Reset = 3Fh]

VOUT is shown in Table 7-3.

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Output Voltage Programming

Table 7-3 VOUT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	NIL	R	0h	This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned.
5-0	VOUT	R/W	3Fh	Output voltage setting or ATRK/DTRK-pin VOUT programming. 0h = 6V 1h = 7V 2h = 8V 3h = 9V 4h = 10V 5h = 11V 6h = 12V 7h = 13V 8h = 14V 9h = 15V Ah = 16V Bh = 17V Ch = 18V Dh = 19V Eh = 20V Fh = 21V 10h = 22V 11h = 23V 12h = 24V 13h = 25V 14h = 26V 15h = 27V 16h = 28V 17h = 29V 18h = 30V 19h = 31V 1Ah = 32V 1Bh = 33V 1Ch = 34V 1Dh = 35V 1Eh = 36V 1Fh = 37V 20h = 38V 21h = 39V 22h = 40V 23h = 41V 24h = 42V 25h = 43V 26h = 44V 27h = 45V 28h = 46V 29h = 47V 2Ah = 48V 2Bh = 49V 2Ch = 50V 2Dh = 51V 2Eh = 52V 2Fh = 53V 30h = 54V 31h = 55V 32h = 56V 33h = 57V 34h = 58V 35h = 59V 36h = 60V 37h = ATRK/DTRK 38h = ATRK/DTRK 39h = ATRK/DTRK 3Ah = ATRK/DTRK 3Bh = ATRK/DTRK 3Ch = ATRK/DTRK 3Dh = ATRK/DTRK 3Eh = ATRK/DTRK 3Fh = ATRK/DTRK

7.2 CONFIGURATION_1 Register (Offset = 1h) [Reset = 04h]

CONFIGURATION_1 is shown in Table 7-4.

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Device Configuration 1

Table 7-4 CONFIGURATION_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	NIL	R	0h	This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned.
5-4	OVP_MAX	R/W	0h	OVP threshold. 0h = 64V 1h = 50V 2h = 35V 3h = 28.5V
3	NFAULT_TWARN	R/W	0h	nFault-pin bahvior on TWARN. 0h = nFAULT-pin not reacting on the thermal warning signal (default) 1h = nFault-pin reacts on thermal warning signal and is pulled low
2-0	VOUT_SLEW	R/W	4h	Output voltage slew rate setting. 0h = no slew rate control 1h = 1 V / 100 us 2h = 1 V / 200 us 3h = 1 V / 400 us 4h = 1 V / 800 us 5h = 1 V / 1.6 ms 6h = 1 V / 3.2 ms 7h = 1 V / 6.4 ms

7.3 CONFIGURATION_2 Register (Offset = 2h) [Reset = 80h]

CONFIGURATION_2 is shown in Table 7-5.

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Device Configuration 2

Table 7-5 CONFIGURATION_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OVP_MAX_LATCH	R/W	1h	Sets the device behavior when the maximum Overvoltage Protection Level (OVP_max) is reached. 0h = 1V Hysteresis 1h = Shutdown and latch
6-5	OPERATION_MODE	R/W	0h	Operation Mode selection (MODE-pin, DEM, FPWM). 0h = MODE-pin 1h = DEM 2h = FPWM 3h = FPWM
4	NFAULT_OVP	R/W	0h	Sets the nFAULT-pin behavior when Undervoltage or Overvoltage is detected. When enabled nFAULT-pin is pulled low when VOUT is above the Overvoltage Protection threshold (OVP or OVP_max) or below the Undervoltage threshold (UV). When disabled nFAULT-pin is only pulled low when VOUT is below the UV (Undervoltage) threshold. 0h = disable 1h = enable
3	ICL_LATCH	R/W	0h	Selects if the device shuts down when peak current limit is exceeded by 20 percent (enabled) or if the device continues operation (disabled). 0h = disable 1h = enable
2	SPREAD_SPECTRUM	R/W	0h	Enabled / disables clock dithering (Spread Spectrum). 0h = disable 1h = enable
1	EN2	R/W	0h	Phase 2 enable. The EN2-pin is overwritten when this bit is set to "1". 0h = EN2-pin 1h = enable phase 2
0	UVLO	R/W	0h	The device behaves as if UVLO/EN is above the UVLO rising threshold when this bit is set to "1". The UVLO function is therefore disabled as long as this bit is set to "1". When the bit is set to "0" the UVLO function is again controlled by the UVLO/EN-pin. 0h = UVLO/EN-pin 1h = overwrite UVLO function

7.4 CONFIGURATION_3 Register (Offset = 3h) [Reset = A1h]

CONFIGURATION_3 is shown in Table 7-6.

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Device Configuration 3

Table 7-6 CONFIGURATION_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	TSDW	R/W	2h	Thermal Shutdown Warning setting. The TSD_WARN flag is set when the delta temperature in respect to TTSD-RISING is reached. 0h = 20°C 1h = 35°C 2h = 50°C 3h = 70°C
5-3	DEAD_TIME	R/W	4h	Dead Time setting. This bit selects the minimum dead time. 0h = 14ns 1h = 30ns 2h = 50ns 3h = 75ns 4h = 100ns 5h = 125ns 6h = 150ns 7h = 200ns
2-0	SINGLE_DUAL	R/W	1h	Single or Dual-chip Configuration. 0h = Single Device; Phase2 = 180°; SYNCIN = off; SYNCOUT = off; SYNCOUT phase shift = off; Clock Dithering = SPREAD_SPECTRUM setting 1h = Single Device ext. clock; Phase2 = 180°; SYNCIN = on; SYNCOUT = off; SYNCOUT phase shift = off; Clock Dithering = disabled 2h = Primary Device; Phase2 = 240°; SYNCIN = off; SYNCOUT = on; SYNCOUT phase shift = 120°; Clock Dithering = SPREAD_SPECTRUM setting 3h = Primary Device; Phase2 = 180°; SYNCIN = off; SYNCOUT = on; SYNCOUT phase shift = 90°; Clock Dithering = SPREAD_SPECTRUM setting 4h = Primary Device ext. clock; Phase2 = 240°; SYNCIN = on; SYNCOUT = on; SYNCOUT phase shift = 120°; Clock Dithering = disabled 5h = Primary Device ext. clock; Phase2 = 180°; SYNCIN = on; SYNCOUT = on; SYNCOUT phase shift = 90°; Clock Dithering = disabled 6h = Secondary Device; Phase2 = 180°; SYNCIN = on; SYNCOUT = off; SYNCOUT phase shift = off; Clock Dithering = disabled 7h = Secondary Device; Phase2 = 180°; SYNCIN = on; SYNCOUT = off; SYNCOUT phase shift = off; Clock Dithering = disabled

7.5 OPERATION_STATE Register (Offset = 4h) [Reset = 00h]

OPERATION_STATE is shown in Table 7-7.

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Device Operation State

Table 7-7 OPERATION_STATE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	NIL	R	0h	This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned.
3-0	STATE	R	0h	This bit shows in which operation state the device is. 0h = Standby 1h = Start Phase 1 & 2 2h = Active DEM 3h = Active FPWM 4h = Bypass 5h = HBx Fault 6h = VCC Fault 7h = FAULT 8h = Thermal Shutdown 9h = VCC CHECK

7.6 STATUS_BYTE Register (Offset = 5h) [Reset = 00h]

STATUS_BYTE is shown in Table 7-8.

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Fault status low byte

Table 7-8 STATUS_BYTE Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CML	R	0h	Communication, Logic, Memory error. 0h = no fault 1h = fault
6	HB_FAULT	R	0h	High side driver UVLO triggered. 0h = no fault 1h = fault
5	ICL_FAULT	R	0h	Peak current limit +20 percent triggered. 0h = no fault 1h = fault
4	ILIM_FAULT	R	0h	Average input current limit triggered. 0h = no fault 1h = fault
3	VOUT_OVP	R	0h	Overvoltage Protection (OVP) triggered. 0h = no fault 1h = fault
2	VOUT_UVP	R	0h	Undervoltage Protection (UVP) triggered. 0h = no fault 1h = fault
1	TSD	R	0h	Thermal Shutdown triggered. 0h = no fault 1h = fault
0	TSD_WARN	R	0h	Thermal Shutdown warning. Device is close to thermal shutdown. 0h = no warning 1h = warning

7.7 CLEAR_FAULTS Register (Offset = 6h) [Reset = 00h]

CLEAR_FAULTS is shown in Table 7-9.

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Clear all latched status flags

Table 7-9 CLEAR_FAULTS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CLEAR_FAULTS	R	0h	Accessing the address is enough to clear the faults in the STATUS_BYTE Register 0x05.