SLVSHB3 November   2025 LM51251A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG-pin)
      2. 6.3.2  Device and Phase Enable/Disable (UVLO/EN, EN2)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Fault Indicator (nFAULT-pin)
      12. 6.3.12 Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
      18. 6.3.18 I2C Features
        1. 6.3.18.1 Register VOUT (0x0)
        2. 6.3.18.2 Register Configuration 1 (0x1)
        3. 6.3.18.3 Register Configuration 2 (0x2)
        4. 6.3.18.4 Register Configuration 3 (0x3)
        5. 6.3.18.5 Register Operation State (0x4)
        6. 6.3.18.6 Register Status Byte (0x5)
        7. 6.3.18.7 Register Clear Faults (0x6)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
    5. 6.5 Programming
      1. 6.5.1 I2C Bus Operation
  8. 7 LM51251A-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Feedback Compensation
      2. 8.1.2 Non-synchronous Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Determine the Total Phase Number
        2. 8.2.2.2  Determining the Duty Cycle
        3. 8.2.2.3  Timing Resistor RT
        4. 8.2.2.4  Inductor Selection Lm
        5. 8.2.2.5  Current Sense Resistor Rcs
        6. 8.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 8.2.2.7  Low-Side Power Switch QL
        8. 8.2.2.8  High-Side Power Switch QH
        9. 8.2.2.9  Snubber Components
        10. 8.2.2.10 Vout Programming
        11. 8.2.2.11 Input Current Limit (ILIM/IMON)
        12. 8.2.2.12 UVLO Divider
        13. 8.2.2.13 Soft Start
        14. 8.2.2.14 CFG Settings
        15. 8.2.2.15 Output Capacitor Cout
        16. 8.2.2.16 Input Capacitor Cin
        17. 8.2.2.17 Bootstrap Capacitor
        18. 8.2.2.18 VCC Capacitor CVCC
        19. 8.2.2.19 BIAS Capacitor
        20. 8.2.2.20 VOUT Capacitor
        21. 8.2.2.21 Loop Compensation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Efficiency
        2. 8.2.3.2 Steady State Waveforms
        3. 8.2.3.3 Step Load Response
        4. 8.2.3.4 Sync Operation
        5. 8.2.3.5 AC Loop Response Curve
        6. 8.2.3.6 Thermal Performance
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5.1 I2C Bus Operation

The CFG-pin sets the device address (8 addresses).

The I2C bus is a communications link between a controller and a series of receiver devices. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the receiver terminals. Each device has an open-drain output to transmit data on the serial data line (SDA). An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. The device hosts a receiver I 2 C interface that supports standard-mode, fast-mode and fast-mode plus operation with data rates up to 100 kbit/s, 400 kbit/s and 1000 kbit/s respectively and auto-increment addressing compatible to I 2 C standard 3.0. Data transmission is initiated with a start bit from the controller as shown in the figure below . The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device receives serial data on the SDA input and check for valid address and control information. If the receiver address bits are set for the device, then the device issues an acknowledge pulse and prepares the receive of register address and data. Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. The I 2 C interfaces auto-sequences through register addresses, so that multiple data words can be sent for a given I 2 C transmission.
LM51251A-Q1 I 2 C START / STOP / ACKNOWLEDGE Protocol Figure 6-30 I 2 C START / STOP / ACKNOWLEDGE Protocol
LM51251A-Q1 I 2 C Data Transmission Timing Figure 6-31 I 2 C Data Transmission Timing
LM51251A-Q1 I 2 C Data Transmission Timing for Maximum Rise/fall Times Figure 6-32 I 2 C Data Transmission Timing for Maximum Rise/fall Times

Clock Stretching

Clock stretching is not supported. If the device is addressed while busy and not able to process the received data, it does not acknowledge the transaction. The device can not acknowledge if the controller initiates an I2C transaction while the device is not completely booted.

Data Transfer Formats

The device supports four different read/write operations:

  • Single read from a defined register address.
  • Single write to a defined register address.
  • Sequential read starting from a defined register address
  • Sequential write starting from a defined register address

Single READ from a Defined Register Address

Figure 6-33 shows the format of a single read from a defined register address. First, the controller issues a start condition followed by a seven-bit I 2 C address. Next, the controller writes a zero to signify that it conducts a write operation. Upon receiving an acknowledge from the receiver the controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the internal I2C register number to the defined value. Then the controller issues a repeat start condition and the seven-bit I2C address followed by a one to signify that it conducts a read operation. Upon receiving a third acknowledge, the controller releases the bus to the device. The device then returns the eight-bit data value from the register on the bus. The controller does not acknowledge (nACK) and issues a stop condition. This action concludes the register read.

LM51251A-Q1 Single READ from a Defined Register Address Figure 6-33 Single READ from a Defined Register Address

Sequential READ Starting from a Defined Register Address

A sequential read operation is an extension of the single read protocol and shown in Figure 6-34. The controller acknowledges the reception of a data byte, the device auto increments the register address and returns the data from the next register. The data transfer is stopped by the controller not acknowledging the last data byte and sending a stop condition.

LM51251A-Q1 Sequential READ Starting from a Defined Register Address Figure 6-34 Sequential READ Starting from a Defined Register Address

Single WRITE to a Defined Register Address

Figure 6-35 shows the format of a single write to a defined register address. First, the controller issues a start condition followed by a seven-bit I2C address. Next, the controller writes a zero to signify that it wishes to conduct a write operation. Upon receiving an acknowledge from the receiver, the controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the I2C register address to the defined value and the controller writes the eight-bit data value. Upon receiving a third acknowledge the device auto increments the I2C register address by one and the controller issues a stop condition. This action concludes the register write.

LM51251A-Q1 Single WRITE to Defined Register Address Figure 6-35 Single WRITE to Defined Register Address

Sequential WRITE Starting from a Defined Register Address

A sequential write operation is an extension of the single write protocol and shown in Figure 6-36. If the controller does not send a stop condition after the device has issued an ACK, the device auto increments the register address by one and the controller can write to the next register.

LM51251A-Q1 Sequential WRITE Starting at a Defined Register Address Figure 6-36 Sequential WRITE Starting at a Defined Register Address