SLVSI60A September   2025  – September 2025 TPS61382-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VCC Power Supply and UVLO Logic
      2. 6.3.2 Enable or Shutdown
      3. 6.3.3 STATUS Pin
        1. 6.3.3.1 Status Indicator IO (STATUS Pin)
        2. 6.3.3.2 Configured as External PMOS Driver
      4. 6.3.4 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Charger Mode Description
        1. 6.4.1.1 Charger Enable
        2. 6.4.1.2 LDO Charger and Buck Charger Description
          1. 6.4.1.2.1 Buck Charger
          2. 6.4.1.2.2 LDO Charger
        3. 6.4.1.3 NiMH Battery Charging Profile
        4. 6.4.1.4 Lithium Battery Charging Profile
        5. 6.4.1.5 Super Capacitor Charging Profile
        6. 6.4.1.6 Battery Cold, Hot Temperature (TS Pin)
        7. 6.4.1.7 Charger Protection and Fault Condition Indication
      2. 6.4.2 Boost Mode Description
        1. 6.4.2.1 Enable and Start up
          1. 6.4.2.1.1 Automatic Transition into Boost Mode
          2. 6.4.2.1.2 Manual Transition into Boost Mode
        2. 6.4.2.2 Down Mode
        3. 6.4.2.3 Output Short- to-Ground Protection
        4. 6.4.2.4 Boost Control Loop
        5. 6.4.2.5 Current Limit Operation
        6. 6.4.2.6 Functional Modes at Light Load
          1. 6.4.2.6.1 Auto PFM Mode
          2. 6.4.2.6.2 Forced PWM Mode
        7. 6.4.2.7 Duty Cycle Limitation
        8. 6.4.2.8 BUB Voltage Loop
        9. 6.4.2.9 Spread Spectrum
      3. 6.4.3 Battery State-of-Health (SOH) Detection Mode Description
        1. 6.4.3.1 SOH Mode Operation
        2. 6.4.3.2 Multi-Signal Output in AVI Pin
        3. 6.4.3.3 Calculate Impedance of Back up Battery
    5. 6.5 I2C Serial Interface
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 Target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multi-Read and Multi-Write
  8. 7 Register Maps
    1. 7.1  Register 00H: CHIP_ID
    2. 7.2  Register 01H: BOOST_SET1
    3. 7.3  Register 02H: BOOST_SET2
    4. 7.4  Register 03H: BOOST_SET3
    5. 7.5  Register 04H: CHGR_SET1
    6. 7.6  Register 05H: CHGR_SET2
    7. 7.7  Register 06H: CHGR_SET3
    8. 7.8  Register 07H: CHGR_SET4
    9. 7.9  Register 08H: CHGR_STATUS
    10. 7.10 Register 09H: SOH_SET1
    11. 7.11 Register 0AH: SOH_SET2
    12. 7.12 Register 0BH: CONTROL_STATUS
    13. 7.13 Register 0CH: FAULT_CONDITION
    14. 7.14 Register 0DH: STATUS_PIN_SET
    15. 7.15 Register 0EH: SW_RST
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the External MOSFET
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Capacitor in Back-Up Battery Side
        4. 8.2.2.4 Selecting the Output Capacitor
        5. 8.2.2.5 Loop Stability and Compensation Design
          1. 8.2.2.5.1 Small Signal Analysis
          2. 8.2.2.5.2 Loop Compensation Design
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6 Register 05H: CHGR_SET2

Figure 7-8 CHGR_SET2
76543210
ReservedBUB_CELLBUB_CC
R-00bR/W-0bR/W-00000b
Figure 7-9 CHGR_SET2 Register Field Descriptions
BitFieldTypeResetDescription

[7:6]

Reserved

R

00b

Reserved
[5]

BUB_CELL

R/W

0b

The number cell of back-up battery

Li-ion supports up to 1s

NiMH supports up to 2s

Super capacitor supports up to 1s

0b=1

1b=2

[4:0]

BUB_CC

R/W

00000b

Set CC current

LDO charger supports 50mA-100mA

Buck charger supports 150mA-3A

00000b=50mA

00001b=100mA

00010b=150mA (Only for NiMH battery)

00011b=200mA (Only for NiMH battery)

00100b=250mA (Only for NiMH battery)

00101b=300mA (Only for NiMH battery)

00110b=350mA (Only for NiMH battery)

00111b=400mA (Only for NiMH battery)

01000b=450mA (Only for NiMH battery)

01001b=500mA

01010b=550mA

01011b=600mA

01100b=650mA

01101b=700mA

01110b=750mA

01111b=800mA

10000b=850mA

10001b=900mA

10010b=950mA

10011b=1A

10100b=1.5A

10101b=2A

10110b=2.5A

10111b=3A