SLVSIC5 September   2026 DRV81315-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Transient thermal impedance and Current capability
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Off state diagnostics (OL, STG)
      2. 6.3.2 Control Interface / Power input
    4. 6.4 Protection Circuits
      1. 6.4.1 Overvoltage clamp
        1. 6.4.1.1 Demagnetization energy capability
          1. 6.4.1.1.1 Single pulse clamping capability
      2. 6.4.2 Overcurrent limit
      3. 6.4.3 Thermal Shutdown (TSD)
        1. 6.4.3.1 Dynamic Overtemperature Stress (ΔTDYN)
        2. 6.4.3.2 Absolute Overtemperature
      4. 6.4.4 Undervoltage Lockout (UVLO)
      5. 6.4.5 Summary of STATUS pin response
  8. 7Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 External components
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
    3. 7.3 Thermal Consideration
      1. 7.3.1 Power Dissipation
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. 9Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Typical values are at TA = 25°C . All limits are over recommended operating conditions, unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES
Iq_off

Supply current in inactive state

IN = 0, DRV81315A

4

10

25

µA
Iq_on

Supply current in active state

IN = 1

25

40

65

µA
Iq_fault

Supply current in fault state

IN = 1

400µA

VUVLO_rise

VDD undervoltage rising

DRV81315A

2.5

2.9

V

IN undervoltage rising

DRV81315

VUVLO_fallVDD undervoltage

falling

DRV81315A

2.3

2.6

V

IN undervoltage falling

DRV81315

STATUS OUTPUT
VSTAT_LStatus output low voltage

ISTAT= 1mA

0.4V
ISTAT_H

Status high leakage current

VSTAT = 5V

1

μA

TWO-LEVEL LOGIC INPUT (DRV81315A)

VIL

Low level logic input

0.8

V

IIL

Low level logic input current

VIN = 0V

-1

1

μA

VIH

High level input voltage

2

V

IIH

High level input current

VIN = 5.5

10

μA

VI_HYS

Input voltage hysteresis

0.13

V

OUTPUT STAGE
RDS(ON)FET on resistanceIO = 1A , TJ = 25°C , VVDD=3V, IN=1, DRV81315A

125

mΩ
IO = 1A , TJ = 25°C, VIN=3V, DRV81315
IO = 1A, TJ = 150°C , VVDD=3V, IN=1, DRV81315A

250

IO = 1A , TJ = 150°C, VIN=3V, DRV81315
RDS(ON)FET on resistanceIO = 1A , TJ = 25°C , VVDD=5V, IN=1, DRV81315A

110

IO = 1A , TJ = 25°C, VIN=5V, DRV81315
IO = 1A, TJ = 150°C , VVDD=5V, IN=1, DRV81315A

220

IO = 1A , TJ = 150°C, VIN=5V, DRV81315
IOFFOff-state leakage current

VOUT = 18 V, TJ = 150°C

5

μA
VF

Body diode forward voltage

IO = -1A

0.8

V

VCLTH_LT

Drain source clamping voltage threshold

IOUT = 10 mA , TJ = -40°C

40

V

VCLAMPDrain source clamping voltageIOUT = 1.5 A , TJ = 150°C

41

45

V

OFF STATE DIAGNOSTIC(DRV81315A)

VOL

Off state open load output detection threshold

IN = 0

0.6

1.2

1.8

V

tOL_DG

Output comparator deglitch

150

μs
SWITCHING
tRRise timeVLOAD = 13V; RL = 13Ω, VIN=5V, DRV81315

20

30

40

μs
VLOAD = 13V; RL = 13Ω, VVDD=5V, DRV81315A
VLOAD = 13V; RL = 13Ω, VIN=3V, DRV81315

20

30

40

VLOAD = 13V; RL = 13Ω, VVDD=3V, DRV81315A
tFFall timeVLOAD = 13V; RL = 13Ω, VIN=5V, DRV81315

15

25

50

μs
VLOAD = 13V; RL = 13Ω, VVDD=5V, DRV81315A
VLOAD = 13V; RL = 13Ω, VIN=3V, DRV81315

30

60

120

VLOAD = 13V; RL = 13Ω, VVDD=3V, DRV81315A

SRrise

Rising slew rate

VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VIN=5V, DRV81315

0.3

0.5

0.7

V/

μs
VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VVDD=5V, DRV81315A
VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VIN=3V, DRV81315

0.3

0.5

0.7

VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VVDD=3V, DRV81315A

SRfall

Falling slew rate

VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VIN=5V, DRV81315

0.3

0.5

0.7

V/

μs
VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VVDD=5V, DRV81315A
VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VIN=3V, DRV81315

0.1

0.25

0.4

VLOAD = 13V; RL = 13Ω, VOUT = 30% VLOAD to 70% VLOAD, VVDD=3V, DRV81315A

tPD_L_to_H

Propogation Delay , Input Low to Output High

VLOAD = 13V; RL = 13Ω, VIN=5V, DRV81315

20

33

40

μs

VLOAD = 13V; RL = 13Ω, VVDD=5V, DRV81315A
VLOAD = 13V; RL = 13Ω, VIN=3V, DRV81315

20

33

40

VLOAD = 13V; RL = 13Ω, VVDD=3V, DRV81315A
tPD_H_to_L

Propogation Delay, Input High to Output Low

VLOAD = 13V; RL = 13Ω, VIN=5V, DRV81315

18

25

45

μs

VLOAD = 13V; RL = 13Ω, VVDD=5V, DRV81315A
VLOAD = 13V; RL = 13Ω, VIN=3V, DRV81315

18

25

45

VLOAD = 13V; RL = 13Ω, VVDD=3V, DRV81315A
PROTECTION CIRCUITS

ILIM

Current limitation value

VINX= 5, TJ = 25°C , DDA package

7.8

10

A

VINX= 5, TJ = 150°C , DDA package

5.5

A

ILIMCurrent limitation valueVINX= 5, TJ = 25°C , DRL package

4.7

6

A

VINX= 5, TJ = 150°C , DRL package

3

A

TTSD

Thermal shutdown temperatureDie temperature150

175

200

°C
TTSD_hysThermal shutdown temperature

hysteresis

7

°C
TSTAT_reset

Thermal reset of Status

135

°C

ΔTJ

Dynamic temperature

40

K

ΔTJ_HYS

Dynamic temperature hysteresis

15

K

tSTATUS

Overtemperature deglitch on STATUS pin

20

μs

Output timing diagrams

DRV81315-Q1 Output rise/fall timesFigure 5-1 Output rise/fall times
DRV81315-Q1 Propogation delayFigure 5-2 Propogation delay