SLVSIC5 September   2026 DRV81315-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Transient thermal impedance and Current capability
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Off state diagnostics (OL, STG)
      2. 6.3.2 Control Interface / Power input
    4. 6.4 Protection Circuits
      1. 6.4.1 Overvoltage clamp
        1. 6.4.1.1 Demagnetization energy capability
          1. 6.4.1.1.1 Single pulse clamping capability
      2. 6.4.2 Overcurrent limit
      3. 6.4.3 Thermal Shutdown (TSD)
        1. 6.4.3.1 Dynamic Overtemperature Stress (ΔTDYN)
        2. 6.4.3.2 Absolute Overtemperature
      4. 6.4.4 Undervoltage Lockout (UVLO)
      5. 6.4.5 Summary of STATUS pin response
  8. 7Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 External components
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
    3. 7.3 Thermal Consideration
      1. 7.3.1 Power Dissipation
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. 9Mechanical, Packaging, and Orderable Information

6.4.5 Summary of STATUS pin response

Table 6-1 Summary of STATUS pin response for DRV81315A
TFET (1)> TTSD TSTAT_reset < TFET < TTSD - TTSD_hys TFET <TSTAT_reset ΔT(2) >ΔTDYN ΔT < ΔTDYN–ΔTDYN_hys

OUT

response		 STATUS

✔

✖

 ✖ ✖ ✔

Off

Low

✖

 ✔ ✖ ✖ ✔

On

Low
✖ ✖ ✔ ✖ ✔ On

High
✖ ✖ ✖ ✖ ✔

On

High
✔ ✖ ✖ ✔ ✖

Off

Low
✖ ✔ ✖ ✔ ✖ Off

Low
✖ ✖ ✔ ✔ ✖ Off Low
✖ ✖ ✖ ✔ ✖ Off High
(1) TFET denotes FET temperature
(2) ΔT= TFET - Tcontroller
Table 6-2 Summary of STATUS pin response for DRV81315
TFET (1)> TTSD TSTAT_reset < TFET < TTSD - TTSD_hys TFET <TSTAT_reset ΔT(2) >ΔTDYN ΔT < ΔTDYN–ΔTDYN_hys OUTresponse STATUS
✔ ✖ ✖ ✖ ✔ Off Low
✖ ✔ ✖ ✖ ✔ On Low
✖ ✖ ✔ ✖ ✔ On Low(3)
✖ ✖ ✖ ✖ ✔ On High
✔ ✖ ✖ ✔ ✖ Off Low
✖ ✔ ✖ ✔ ✖ Off Low
✖ ✖ ✔ ✔ ✖ Off Low
✖ ✖ ✖ ✔ ✖ Off High
(1) TFET denotes FET temperature
(2) ΔT= TFET - Tcontroller
(3) Latched low till IN is toggled