SLVSII7 December   2025 TPSM8D7420 , TPSM8D7620

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC)
      3. 7.3.3  Device Configuration Pin (MSEL)
      4. 7.3.4  Multiphase Output Configuration
      5. 7.3.5  Enable and Adjustable UVLO
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Device Synchronization (SYNC)
        1. 7.3.7.1 Clock Locking
      8. 7.3.8  Adjustable Output Voltage (FB)
      9. 7.3.9  Control Loop Compensation (COMP)
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power-Good Output Voltage Monitoring
      12. 7.3.12 Output Discharge
      13. 7.3.13 Soft-Start (SS)
      14. 7.3.14 Overcurrent Protection (OCP)
      15. 7.3.15 Temperature Output
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 Setting the Output Voltage
        4. 8.2.2.4 Integrated Inductor Considerations
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 VCC and BOOT Capacitors
        7. 8.2.2.7 Output Capacitor Selection
        8. 8.2.2.8 Compensation Selection
      3. 8.2.3 Application Curves
    3. 8.3 2-PH Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves 2-PH
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

TPSM8D7420 TPSM8D7620 56-Pin FCCSP, APT Package (Top View) Figure 5-1 56-Pin FCCSP, APT Package (Top View)
Legend
VINx PGND
VOUTx All other pins
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
D5, D6, D7 VIN1 I Input supply to the regulator. Place decoupling input capacitors from the VIN pins to PGND pins as close as possible. There is an internal 100nF high-frequency decoupling from VIN to PGND on each channel of the module.
D1, D2, D3 VIN2
F7, G6, G7, H6, H7 VOUT1 O VOUT power connection. Connect the output capacitors from VOUT to PGND close to the module output pins.
F1, G1, G2, H1, H2 VOUT2
C1, C2, C3, C4, C5, C6, C7, D4, E3, E4, E5, F3, F4, F5, G3, G4, G5, H3, H4, H5 PGND G Ground return for the power stage. This pin is internally connected to the source of the low-side MOSFET.
E6 BOOT1 I/O Supply for the internal high-side MOSFET gate driver. Connected to an internal 100nF capacitor between SW and BOOT. Monitoring connection only, use as NC in design.
E2 BOOT2
F6 SW1 O Switch node of the module. Monitoring connection only, use as NC in design.
F2 SW2
B7 SYNC I An external clock can be applied to this pin to synchronize the switching frequency.
B1 SYNC_ OUT O Synchronization output signal. Monitoring connection only, use as NC in design or as SYNC for another regulator.
A7 MSEL I/O Multi-function select pin. A resistor from the MSEL pin to AGND selects between internal and external compensation and sets the channel configuration and phase. A ±1% tolerance resistor is required. After startup, this pin becomes an analog temperature output.
E7 EN1 I Enable pin. An active high input to EN enables VOUT. EN must never be left floating.
E1 EN2
B4 VCC P Internal LDO regulator output. An internal 2.2μF capacitor is connected between VCC1, VCC2 and AGND1, AGND2 respectively. VCC can be used as a pullup for PG. Otherwise leave VCC floating.
A6 FB1 I Feedback pin for output voltage regulation. Connect this pin to the midpoint of the resistor divider to set the output voltage. A ±1% tolerance resistor or better is recommended.
A2 FB2
A4 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
A1 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 400kHz and 2.2MHz. A ±1% tolerance resistor is recommended.
B6 SS1 I Connect a capacitor to AGND to set the SS time.
B2 SS2
A5 COMP1 I/O Output of the GM error amplifier in external compensation mode. Current sharing signal in multiphase mode. Can be left floating for internal compensation mode.
A3 COMP2
B5 PG1 O Open-drain power-good status signal. Connect an external pullup resistor to a voltage source. When the FB voltage moves outside the specified limits, PG goes low after the specified delay.
B3 PG2
(1) I = input, O = output, P = power, G = ground, N/A = not applicable