SLVSII7 December   2025 TPSM8D7420 , TPSM8D7620

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC)
      3. 7.3.3  Device Configuration Pin (MSEL)
      4. 7.3.4  Multiphase Output Configuration
      5. 7.3.5  Enable and Adjustable UVLO
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Device Synchronization (SYNC)
        1. 7.3.7.1 Clock Locking
      8. 7.3.8  Adjustable Output Voltage (FB)
      9. 7.3.9  Control Loop Compensation (COMP)
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power-Good Output Voltage Monitoring
      12. 7.3.12 Output Discharge
      13. 7.3.13 Soft-Start (SS)
      14. 7.3.14 Overcurrent Protection (OCP)
      15. 7.3.15 Temperature Output
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 Setting the Output Voltage
        4. 8.2.2.4 Integrated Inductor Considerations
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 VCC and BOOT Capacitors
        7. 8.2.2.7 Output Capacitor Selection
        8. 8.2.2.8 Compensation Selection
      3. 8.2.3 Application Curves
    3. 8.3 2-PH Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves 2-PH
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Over recommended input voltage range, TJ = –40°C to +125°C. Typical values are at TJ = 25°C and VIN = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current in VIN1 + VIN2, multiphase mode Non-switching, VEN = 2V, MSEL=41.2kΩ, RT=6.8kΩ, SS=0V 2 4.9 mA
IQ Quiescent current in VIN1 + VIN2, multi-output mode Non-switching, VEN = 2V, MSEL=29.4kΩ, RT=6.8kΩ, SS=0V 4.3 8.2 mA
ISD Shutdown supply current in VIN1 + VIN2 VEN = 0V 2 10.1 µA
UVLO
VINUVLO(R) VIN UVLO rising threshold VIN rising 3.5 3.8 V
VINUVLO(F) VIN UVLO falling threshold VIN falling 2.5 3 V
VINUVLO(H) VIN UVLO hysteresis 1.2 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.125 1.25 1.375 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.75 0.84 1.0 V
VEN(H) EN voltage hysteresis 0.25 0.4 0.55 V
VEN(W) EN voltage wake-up threshold 0.4 V
IEN EN pin sourcing current post EN rising threshold VEN = VIN = 12V 400 nA
INTERNAL LDO
VVCC Internal LDO output voltage VIN ≥ 5V, IVCC ≤ 100mA 4 4.4 5 V
IVCC Internal LDO short-circuit current limit VIN = 12V 130 220 mA
REFERENCE VOLTAGE
VFB_INT FB reference voltage Internal compensation selected, no load current. 595.5 600 604.5 mV
VFB_EXT FB reference voltage External compensation selected, VCOMP = 0.6V 595.5 600 604.5 mV
IFB(LKG) FB input leakage current VFB = 0.6V 10 250 nA
ERROR AMPLIFIER
gm-ext EA transconductance - External Comp VFB = VCOMP 840 1000 1150 µS
ICOMP(src) EA source current - External Comp VCOMP = 1V, VFB = 0.4V 100 155 400 µA
ICOMP(sink) EA sink current - External Comp VCOMP = 1V, VFB = 0.8V 50 155 500 µA
SWITCHING FREQUENCY
fSW-max(FCCM) Switching frequency, FCCM operation RRT = 6.81kΩ to AGND 1.95 2.2 2.4 MHz
fSW(FCCM) Adjustable switching frequency range RRT resistor from 6.81kΩ to 39.2kΩ to AGND 0.4 2.2 MHz
SYNCHRONIZATION
VIH(sync) SYNC High-Level Threshold 1.25 1.5 V
VIL(sync) SYNC Low-Level Threshold 0.65 1.0 V
VOH(sync) Sync output high voltage min No loading on SYNC_OUT pin 4.4 V
VOL(sync) Sync output low voltage max No loading on SYNC_OUT pin 0.6 V
fSYNC-2p2 Frequency sync range around 2.2MHz RRT = 6.81kΩ to AGND 1.76 2.2 2.64 MHz
fSYNC-0p4 Frequency sync range around 400kHz RRT = 39.2kΩ to AGND 320 400 480 kHz
tSYNC(IH) Minimum pulse width of external synchronization signal above VIH(sync) 50 ns
tSYNC(IL) Minimum pulse width of external synchronization signal below VIL(sync) 50 ns
tSYNC-SW(delay) Delay from SYNC rising edge to SW rising edge 40 ns
STARTUP
ISS(R) Soft-start charge current VSS = 0 V 21 µA
tEN EN HIGH to start of switching delay VIN > VINUVLO(R) 1300 µs
RSS(F) Soft-start discharge resistance 22 45 Ω
POWER STAGE
tON(min) Minimum ON pulse width (1) VIN = 12V 45 60 ns
tOFF(min) Minimum OFF pulse width (1) VIN = 4V 60 105 ns
OVERCURRENT PROTECTION
IHS(OC1) High-side peak current limit TPSM8D7620 Peak current limit on HS FET 8.2 9 9.6 A
IHS(OC2) High-side peak current limit TPSM8D7420 Peak current limit on HS FET 6.3 7.2 8.2 A
ILS(OC1) Low-side valley current limit TPSM8D7620 Valley current limit on LS FET 5.9 6.8 7.2 A
ILS(OC2) Low-side valley current limit TPSM8D7420 Valley current limit on LS FET 4.4 5.4 6.4 A
ILS1(NOC) Low-side negative current limit TPSM8D7620 Sinking current limit on LS FET –4 –3 A
ILS3(NOC) Low-side negative current limit TPSM8D7420 Sinking current limit on LS FET –3.5 –2.5 A
VHiccup-FB Hiccup threshold on FB pin HS FET On-time > 165 ns 0.18 0.23 0.3 V
tHiccup-1 Wait time before entering Hiccup 126 128 130 Curent Limit cycles
tHiccup-2 Hiccup time before re-start 50 70 ms
OUTPUT DISCHARGE
RDischarge Output discharge resistance VIN = 12V, VOUT = 2.5V, power conversion disabled 19.5 Ω
POWER GOOD
VPGTH-1 Power-Good threshold (PG) PGOOD low, VFB rising 93 96 99 % VREF
VPGTH-2 Power-Good threshold (PG) PGOOD high, VFB falling  91 93 95
% VREF
 
VPGTH-3 Power-Good threshold (PG) PGOOD high, VFB rising 109 113 117
% VREF
 
VPGTH-4 Power-Good threshold (PG) PGOOD low, VFB falling 107 110 113
% VREF
 
tPGOOD(R) PG delay from VFB valid to PGOOD high VVOUT = 3.3V 300 700 µs
tPGOOD(F) PG delay from VFB invalid to PGOOD low VVOUT = 3.3V 47 µs
IPG(LKG) PG pin Leakage current when open drain output is high VPG = 3.3 V 0.075 µA
VPG-D(LOW) PG pin output low-level voltage for both channels  IPG = 1 mA, VEN = 0 V, VIN > VIN(PG_VALID).  400 mV
RPG Pull Down MOSFET Resistance IPG = 1 mA, VEN = 3.3 V. 35 90 Ω
VIN(PG_VALID) Minimum VIN for valid PG output Pull up resistance on PG - RPG = 10 kΩ, Voltage Pull up on PG - VPULLUP_PG=3V, VPG-D(LOW)=0.4V 1.2 V
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising 153 167 186 °C
TJ(HYS) Thermal shutdown hysteresis (1) 9 °C
Tsense TEMP sensing accuracy (1) After calibration at TA=25°C –10 +10 °C
(1) Verified by design.