SLVSIJ3 May   2026 DRV81646-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7.     13
    8. 5.7 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Interface and Slew Rate (RSLEW/CNTL)
      2. 6.3.2 Current Sensing With FET Source Terminals
      3. 6.3.3 Integrated Clamp Diode, VCLAMP
      4. 6.3.4 Protection Circuits
        1. 6.3.4.1 ILIM Analog Current Limit
          1. 6.3.4.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.4.2 Cut-Off Delay (COD)
        3. 6.3.4.3 INRUSH Mode
        4. 6.3.4.4 Thermal Shutdown (TSD)
        5. 6.3.4.5 Undervoltage Lockout (UVLO)
      5. 6.3.5 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
      3. 6.4.3 SPI Mode
        1. 6.4.3.1 Parity Bit Calculation
        2. 6.4.3.2 SPI Input Packet
        3. 6.4.3.3 SPI Response Packet
        4. 6.4.3.4 SPI Error Reporting
        5. 6.4.3.5 SPI Daisy Chain
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
    3. 7.3 Application Curves
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Bulk Capacitance
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

6.4.3.3 SPI Response Packet

Table 6-10 SPI Response Packet
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FAULT_CH4 CH4_State FAULT_CH3 CH3_State FAULT_CH2 CH2_State FAULT_CH1 CH1_State

The current channel states of individual channels are latched on the falling edge of the nSCS pin (when SPI transaction is initiated). Latched faults are cleared on rising edge of the nSCS pin.

Table 6-11 FAULT_CHx Bit Description
FAULT_CHx DESCRIPTION
0 Channel is working normally since last SPI transaction
1 Fault occurred on channel X. This bit is set if channel X encountered a fault since the last SPI transaction. The bit clears when NSCS is pulled back high at the end of valid SPI transaction ( parity checks pass).