SLVSIJ3 May   2026 DRV81646-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7.     13
    8. 5.7 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Interface and Slew Rate (RSLEW/CNTL)
      2. 6.3.2 Current Sensing With FET Source Terminals
      3. 6.3.3 Integrated Clamp Diode, VCLAMP
      4. 6.3.4 Protection Circuits
        1. 6.3.4.1 ILIM Analog Current Limit
          1. 6.3.4.1.1 Effect of Load Resistance on Power Dissipation Before TSD
        2. 6.3.4.2 Cut-Off Delay (COD)
        3. 6.3.4.3 INRUSH Mode
        4. 6.3.4.4 Thermal Shutdown (TSD)
        5. 6.3.4.5 Undervoltage Lockout (UVLO)
      5. 6.3.5 Fault Conditions Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Interface Operation
      2. 6.4.2 Parallel Outputs
      3. 6.4.3 SPI Mode
        1. 6.4.3.1 Parity Bit Calculation
        2. 6.4.3.2 SPI Input Packet
        3. 6.4.3.3 SPI Response Packet
        4. 6.4.3.4 SPI Error Reporting
        5. 6.4.3.5 SPI Daisy Chain
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 External Components
      2. 7.2.2 Continuous Current Capability
      3. 7.2.3 Power Dissipation
    3. 7.3 Application Curves
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Bulk Capacitance
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

7.2.2 Continuous Current Capability

Table 7-3 below shows an estimation of the continuous current ability of each channel with different numbers of channels on for different ambient temperatures. Row 1 Channel on illustrates the continuous current ability if 1 OUT is on, and the other 3 outputs are off. Row 2 Channels on illustrates if 2 channels are on with an equal load and the other two outputs are off. Row 4 Channels on illustrates if all 4 channels are on simultaneously with an equal load on each one. For example, with 4 Channels on each channel can output 2.5A for a total of 10.0A running through the device.

This data is from bench tests on a large PCB with layout optimized for power dissipation, the continuous current capability is different for every system and PCB design.

Table 7-3 FET DC Current Capability per OUTx - DGQ Package
Setup 25°C 55°C 85°C 125°C
1 Channel on 3.4A 3.1A 2.9A 2.4A
2 Channels on 3.1A 2.7A 2.4A 1.8A
4 Channels on 2.5A 2.2A 1.7A 1.3A

Note that this only applies for loads that are continuous ON, not PWM. Switching the outputs with PWM introduces switching losses which further heat the device and results in significantly less average current capability.