SLVSIN9 June   2026 LM25192-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable ILIM
      11. 7.3.11 IOUT Monitor
      12. 7.3.12 Cable Drop Compensation
      13. 7.3.13 Slope Compensation
      14. 7.3.14 Shunt Current Sensing
      15. 7.3.15 Hiccup Mode Current Limiting
      16. 7.3.16 Device Configuration (CNFG)
      17. 7.3.17 Pulse Frequency Modulation (PFM) / Synchronization
      18. 7.3.18 Out-of-Audio Operation
      19. 7.3.19 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
  9. 8 Programming
    1. 8.1 I2C Bus Operation
    2. 8.2 Clock Stretching
    3. 8.3 Data Transfer Formats
    4. 8.4 Single READ from a Defined Register Address
    5. 8.5 Sequential READ Starting from a Defined Register Address
    6. 8.6 Single WRITE to a Defined Register Address
    7. 8.7 Sequential WRITE Starting at a Defined Register Address
  10. 9 LM25192-Q1 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Powertrain Components
        1. 10.1.1.1 Buck Inductor
        2. 10.1.1.2 Output Capacitors
        3. 10.1.1.3 Input Capacitors
        4. 10.1.1.4 Power MOSFETs
        5. 10.1.1.5 EMI Filter
      2. 10.1.2 Error Amplifier and Compensation
    2. 10.2 Typical Application
      1. 10.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Buck Inductor
          2. 10.2.1.2.2 Current-Sense Resistance
          3. 10.2.1.2.3 Output Capacitors
          4. 10.2.1.2.4 Input Capacitors
          5. 10.2.1.2.5 Compensation Components
        3. 10.2.1.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Power Stage Layout
        2. 10.4.1.2 Gate-Drive Layout
        3. 10.4.1.3 PWM Controller Layout
        4. 10.4.1.4 Thermal Design and Layout
        5. 10.4.1.5 Ground Plane Design
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 PCB Layout Resources
        2. 11.2.1.2 Thermal Design Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

7.3.17 Pulse Frequency Modulation (PFM) / Synchronization

The LM25192-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for Pulse Frequency Modulation(PFM), the low-side MOSFET is switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss during light load operation. Note that configuring the device for PFM has an effect of slower response to load transients during light load operation.

The diode emulation feature is configured with the PFM / SYNC pin. To enable diode emulation and achieve discontinuous conduction mode (DCM) operation at light loads, connect PFM / SYNC to VDDA. If forced pulse-width modulation (FPWM) or continuous conduction mode (CCM) operation is desired, tie PFM / SYNC to AGND. Note that diode emulation is automatically engaged to prevent reverse current flow during a prebias start-up in PFM. During start-up, when the output voltage approaches the regulation set point a gradual change from DCM to CCM occurs, preventing the output voltage overshoot. Changing the mode of operation dynamically is possible, however, the rate of change must be < 10Hz. The time to transition from PFM to FPWM operation is dependent on the output load current. In a typical application, the transition from PFM to FPWM operation occurs in less than 1ms if the output current is greater than 100mA. Similarly, for the output currents of around 1mA, the transition generally occurs in tens of milliseconds. This transition can be sped up by enabling output active discharge during the transition between PFM and FPWM by setting the ACTIVE_DISCHARGE_CFG2 bit high in register 0xD2. This output active discharge current can be set from 24mA – 72mA through register 0xD2 and is only enabled until the transition to FPWM is complete, which typically takes several hundred microseconds.

To synchronize the LM25192-Q1 to an external source, apply a logic-level clock (greater than 2V) to the PFM / SYNC pin. The LM25192-Q1 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.2MHz. Under low VIN conditions when the minimum off-time is reached, the synchronization signal is ignored, allowing the switching frequency to be reduced to maintain output voltage regulation.

When operating in PFM mode, TI does not recommend to operate the part with an output voltage above 22V when the SEL_FB_DIV20 bit is set low.