SLVSIN9 June   2026 LM25192-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable ILIM
      11. 7.3.11 IOUT Monitor
      12. 7.3.12 Cable Drop Compensation
      13. 7.3.13 Slope Compensation
      14. 7.3.14 Shunt Current Sensing
      15. 7.3.15 Hiccup Mode Current Limiting
      16. 7.3.16 Device Configuration (CNFG)
      17. 7.3.17 Pulse Frequency Modulation (PFM) / Synchronization
      18. 7.3.18 Out-of-Audio Operation
      19. 7.3.19 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
  9. 8 Programming
    1. 8.1 I2C Bus Operation
    2. 8.2 Clock Stretching
    3. 8.3 Data Transfer Formats
    4. 8.4 Single READ from a Defined Register Address
    5. 8.5 Sequential READ Starting from a Defined Register Address
    6. 8.6 Single WRITE to a Defined Register Address
    7. 8.7 Sequential WRITE Starting at a Defined Register Address
  10. 9 LM25192-Q1 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Powertrain Components
        1. 10.1.1.1 Buck Inductor
        2. 10.1.1.2 Output Capacitors
        3. 10.1.1.3 Input Capacitors
        4. 10.1.1.4 Power MOSFETs
        5. 10.1.1.5 EMI Filter
      2. 10.1.2 Error Amplifier and Compensation
    2. 10.2 Typical Application
      1. 10.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Buck Inductor
          2. 10.2.1.2.2 Current-Sense Resistance
          3. 10.2.1.2.3 Output Capacitors
          4. 10.2.1.2.4 Input Capacitors
          5. 10.2.1.2.5 Compensation Components
        3. 10.2.1.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Power Stage Layout
        2. 10.4.1.2 Gate-Drive Layout
        3. 10.4.1.3 PWM Controller Layout
        4. 10.4.1.4 Thermal Design and Layout
        5. 10.4.1.5 Ground Plane Design
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 PCB Layout Resources
        2. 11.2.1.2 Thermal Design Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.5 Sequential READ Starting from a Defined Register Address

A sequential read operation is an extension of the single read protocol and shown in Figure 8-5. The controller acknowledges the reception of a data byte, and the device auto increments the register address and returns the data from the next register. The data transfer is stopped by the controller not acknowledging the last data byte and sending a stop condition.


LM25192-Q1 Sequential READ Starting from a Defined Register Address
Figure 8-5 Sequential READ Starting from a Defined Register Address