SLVSJ99A July   2025  – June 2026 TPLD2001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  I/O Pins
        1. 8.3.1.1 Input Modes
        2. 8.3.1.2 Output Modes
        3. 8.3.1.3 Pull-Up or Pull-Down Resistors
      2. 8.3.2  Connection Mux
      3. 8.3.3  Configurable Use Logic Blocks
        1. 8.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 8.3.3.1.1 2-Bit LUT
          2. 8.3.3.1.2 D Flip-Flop/Latch
        2. 8.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 8.3.3.2.1 2-Bit LUT
          2. 8.3.3.2.2 Pattern Generator
        3. 8.3.3.3 3-Bit LUT or D Flip-Flop/Latch With Reset/Set Macro-Cell
          1. 8.3.3.3.1 3-bit LUT
          2. 8.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 8.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 8.3.3.4.1 3-bit LUT
          2. 8.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 8.3.3.4.3 8-bit Shift Register
        5. 8.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set Macro-Cell
          1. 8.3.3.5.1 4-bit LUT
          2. 8.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 8.3.4  Configurable Logic and Timing Blocks
        1. 8.3.4.1 3-bit LUT
        2. 8.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 8.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 8.3.4.3.1 Delay Mode
          2. 8.3.4.3.2 Reset Counter Mode
          3. 8.3.4.3.3 One-Shot Mode
          4. 8.3.4.3.4 Frequency Detector Mode
          5. 8.3.4.3.5 Edge Detector Mode
          6. 8.3.4.3.6 Delayed Edge Detector Mode
        4. 8.3.4.4 LUT/DFF + CNT modes
      5. 8.3.5  Programmable Deglitch Filter or Edge Detector
      6. 8.3.6  Deglitch Filter or Edge Detector
      7. 8.3.7  State Machine (SM)
        1. 8.3.7.1 State Machine Inputs
        2. 8.3.7.2 State Machine Outputs
        3. 8.3.7.3 Configuring the State Machine
        4. 8.3.7.4 State Machine Timing Considerations
      8. 8.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 8.3.9  PWM Generators
      10. 8.3.10 Watchdog Timer
      11. 8.3.11 Analog Comparators
        1. 8.3.11.1 Discrete Analog Comparator (ACMP)
        2. 8.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 8.3.12 Voltage Reference (VREF)
      13. 8.3.13 Analog Temperature Sensor (TS)
      14. 8.3.14 Analog Multiplexer (AMUX)
      15. 8.3.15 Oscillators
        1. 8.3.15.1 2kHz Fixed Frequency Oscillator
        2. 8.3.15.2 2MHz Fixed Frequency Oscillator
        3. 8.3.15.3 25MHz Fixed Frequency Oscillator
        4. 8.3.15.4 Oscillator Power Modes
      16. 8.3.16 Serial Communications
        1. 8.3.16.1 I2C Mode
        2. 8.3.16.2 SPI Mode
        3. 8.3.16.3 Virtual I/Os
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Power Supply Control Modes
      3. 8.4.3 Protection Features
        1. 8.4.3.1 Device Read/Write Lock
        2. 8.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 8.4.4 Programming
        1. 8.4.4.1 Selectable I2C/SPI
        2. 8.4.4.2 Configuration Memory and One-Time Programmable Memory Programming
        3. 8.4.4.3 Intel HEX File Format
  10. 9  TPLD2001-Q1 Registers
    1. 9.1 TPLD2001_User Registers
    2. 9.2 TPLD2001_Cfg_0 Registers
    3. 9.3 TPLD2001_Cfg_1 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power Considerations
        2. 10.2.1.2 Input Considerations
        3. 10.2.1.3 Output Considerations
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell

This configurable use logic block can serve as either a 3-bit LUT or as a D flip-flop or latch with a reset or set or an 8-bit Shift register.

TPLD2001-Q1 3-bit LUT or DFF/Latch with nRST/nSET or 8-bit SISO Shift Register Block Diagram Figure 8-7 3-bit LUT or DFF/Latch with nRST/nSET or 8-bit SISO Shift Register Block Diagram