SLVSJA1 August   2025 DLP800XE

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Timing Requirements
    9.     15
    10. 5.8  System Mounting Interface Loads
    11.     17
    12. 5.9  Micromirror Array Physical Characteristics
    13.     19
    14. 5.10 Micromirror Array Optical Characteristics
    15.     21
    16. 5.11 Window Characteristics
    17. 5.12 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 8.1 DMD Power Supply Requirements
    2. 8.2 DMD Power Supply Power-Up Procedure
    3. 8.3 DMD Power Supply Power-Down Procedure
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
        1. 9.2.3.1 Voltage Signals
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
    3. 10.3 Device Markings
    4. 10.4 Documentation Support
      1. 10.4.1 Related Documentation
    5. 10.5 Receiving Notification of Documentation Updates
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MINNOMMAXUNIT
VOLTAGE SUPPLY
VDDSupply voltage for LVCMOS core logic(1)1.651.81.95V
VDDISupply voltage for LVDS Interface(1)1.651.81.95V
VCC2Micromirror Electrode and HVCMOS voltage(1)(2)9.51010.5V
VMBRSTMicromirror Bias / Reset Voltage(1)–1721.5V
|VDD – VDDI|Supply voltage delta (absolute value)(3)00.3V
LVCMOS
VIH(DC)Input High Voltage0.7 × VDDVDD + 0.3V
VIL(DC)Input Low Voltage–0.30.3 × VDDV
VIH(AC)Input High Voltage0.8 × VDDVDD + 0.3V
VIL(AC)Input Low Voltage–0.30.2 × VDDV
IOHHigh-level Output Current2mA
IOLLow-level Output Current–2mA
tPWRDNZPWRDNZ pulse width(4)10ns
SCP INTERFACE
FSCPCLKSCP clock frequency50500kHz
SCPCLKDCDINSCP Clk Input duty cycle40%60%
LVDS INTERFACE
FCLOCKClock frequency for LVDS interface (all channels), DCLK(5)400MHz
DCDINInput CLK Duty Cycle Distortion tolerance44%56%
|VID|Input differential voltage (absolute value)(6)150300440mV
VCMCommon mode voltage(6)110012001300mV
VLVDSLVDS voltage(6)8801520mV
tLVDS_RSTZTime required for LVDS receivers to recover from PWRDNZ2µs
ZINInternal differential termination resistance80100120Ω
ZLINELine differential impedance (PWB/trace)90100110Ω
ENVIRONMENTAL
TARRAYArray temperature, long-term operational(7)(8)(9)1040 to 70(10)°C
Array temperature, short-term operational, 500 hour max(9)(11)010°C
TDP -AVGAverage dew point average temperature (non–condensing)(12)28°C
TDP-ELRElevated dew point temperature range (non-condensing)(13)2836°C
CTELRCumulative time in elevated dew point temperature range24Months
QAP-ILLWindow aperture illumination overfill(14)(15)(16)17W/cm2
SOLID STATE ILLUMINATION
ILLUVIllumination power at wavelengths < 410nm(7)(18)10mW/cm2
ILLVISIllumination power at wavelengths ≥ 410nm and ≤ 800nm(17)(18) 22W/cm2
ILLIRIlumination power at wavelengths > 800nm(18)10mW/cm2
ILLBLUIllumination power at wavelengths ≥ 410nm and ≤ 475nm(17)(18)7.5W/cm2
ILLBLU1Illumination power at wavelengths ≥ 410nm and ≤ 440nm(17)(18)1.1W/cm2
All voltages are referenced to common ground VSS. VDD, VDDI, and VCC2 power supplies are all required for proper DMD operation. VSS must also be connected.
VCC2 supply transients must fall within the specified max voltages.
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit. See the DMD Power Supply Requirements
PWRDNZ input pin resets the SCP and disables the LVDS receivers. The PWRDNZ input pin overrides the SCPENZ input pin and tristates the SCPDO output pin.
See LVDS clock timing requirements in Timing Requirements.
See LVDS Waveform Parameters for the LVDS waveform requirements.
Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduce device lifetime.
Long-term is defined as the usable life of the device.
The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), shown in Figure 6-1 , using the Micromirror Array Temperature Calculation.
Per Figure 5-1, the maximum operational array temperature is derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Micromirror Landed-on/Landed-off Duty Cycle for a definition of micromirror landed duty cycle.
Short-term is the total cumulative time over the useful life of the device.
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
Exposure to dew point temperatures in the elevated range during storage and operation is limited to less than a total cumulative time of CTELR.
Applies to the region defined in Figure 5-2
The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view.  The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. Minimizing the light flux incident outside the active array is a design requirement of the illumination optical system. Depending on the particular optical architecture and assembly tolerances of the optical system, the amount of overfill light on the outside of the active array may cause system performance degradation.
The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (TARRAY).