SLVSKG8A April   2026  – June 2026 BQ25853-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Power-On-Reset
      2. 7.3.2  Device Power-Up From Battery Without Input Source
      3. 7.3.3  Device Power Up from Input Source
        1. 7.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 7.3.3.2 MODE Pin Configuration
        3. 7.3.3.3 REGN Regulator (REGN LDO)
        4. 7.3.3.4 Compensation-Free Buck-Boost Converter Operation
          1. 7.3.3.4.1 Light-Load Operation
        5. 7.3.3.5 Switching Frequency and Synchronization (FSW_SYNC)
        6. 7.3.3.6 Device HIZ Mode
      4. 7.3.4  Battery Charging Management
        1. 7.3.4.1 Autonomous Charging Cycle
          1. 7.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 7.3.4.2 Li-Ion Battery Charging Profile
        3. 7.3.4.3 LiFePO4 Battery Charging Profile
        4. 7.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 7.3.4.5 Charging Safety Timer
        6. 7.3.4.6 Thermistor Qualification
          1. 7.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 7.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 7.3.5  Power Management
        1. 7.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 7.3.5.1.1 Input Current Regulation
            1. 7.3.5.1.1.1 ILIM_HIZ Pin
          2. 7.3.5.1.2 Input Voltage Regulation
      6. 7.3.6  Switching Frequency Dithering Feature
      7. 7.3.7  Reverse Mode Power Direction
        1. 7.3.7.1 Auto Reverse Mode
      8. 7.3.8  Integrated 16-Bit ADC for Monitoring
      9. 7.3.9  Status Outputs (PG, STAT and INT)
        1. 7.3.9.1 Power Good Indicator (PG)
        2. 7.3.9.2 Charging Status Indicator (STAT Pin)
        3. 7.3.9.3 Interrupt to Host (INT)
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring
          1. 7.3.10.1.1 VAC Over-voltage Protection (VAC_OVP)
          2. 7.3.10.1.2 VAC Under-voltage Protection (VAC_UVP)
          3. 7.3.10.1.3 Battery Over-current Protection (BAT_OCP)
          4. 7.3.10.1.4 Reverse Mode Over-voltage Protection (REV_OVP)
          5. 7.3.10.1.5 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
          6. 7.3.10.1.6 REGN Under-voltage Protection (REGN_OKZ)
        2. 7.3.10.2 Thermal Shutdown (TSHUT)
      11. 7.3.11 Serial Interface
        1. 7.3.11.1 Data Validity
        2. 7.3.11.2 START and STOP Conditions
        3. 7.3.11.3 Byte Format
        4. 7.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.11.5 Target Address and Data Direction Bit
        6. 7.3.11.6 Single Write and Read
        7. 7.3.11.7 Multi-Write and Multi-Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 BQ25853Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 8.2.1.2.2 Charge Voltage Selection
          3. 8.2.1.2.3 Reverse Mode System Voltage Selection
          4. 8.2.1.2.4 Switching Frequency Selection
          5. 8.2.1.2.5 Inductor Selection
          6. 8.2.1.2.6 Input (VAC / SYS) Capacitor
          7. 8.2.1.2.7 Output (VBAT) Capacitor
          8. 8.2.1.2.8 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          9. 8.2.1.2.9 Power MOSFETs Selection
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.6 Switching Frequency Dithering Feature

Normally, the IC switches in fixed frequency which can be adjusted through FSW_SYNC pin. The charger also supports frequency dithering to improve EMI performance and help pass the IEC-CISPR 32 specification. Dithering is disabled by default as EN_DITHER=00b at startup. Dithering can be enabled by setting EN_DITHER=01/10/11b. The switching frequency is not fixed when dithering is enabled and varies within determined range by setting EN_DITHER to 01/10/11b, which corresponds to ±2%/4%/6% switching frequency variation. A larger dithering range results in a smaller EMI noise peak, but a larger dithering range also causes slightly more output voltage ripple. Therefore, the dithering frequency range selection is a trade-off between EMI noise peak and output voltage ripple and we recommend you to select the lowest dithering range which can pass IEC-CISPR 32 specification. The patented dithering pattern can improve EMI performance in the switching frequency up to 30MHz range which covers the entire conductive EMI noise range.

Note that the Dithering feature does not work if an external clock is provided.