SLVSLR7 May   2026 DRV8762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions 48-Pin DRV8762-Q1
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information 1pkg
    4. 5.4 Electrical Characteristics
    5. 5.5 SPI Timing Requirements
    6. 5.6 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 H-Bridge Gate Driver
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 4x PWM Mode
          2. 6.3.1.1.2 2x PWM Mode with INLx enable control
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 VCP Trickle Charge pump
          3. 6.3.1.2.3 Gate Driver Output
          4. 6.3.1.2.4 Passive and Semi-active pull-down resistor
          5. 6.3.1.2.5 TDRIVE/IDRIVE Gate Drive Timing Control
          6. 6.3.1.2.6 Propagation Delay
          7. 6.3.1.2.7 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 DVDD Linear Voltage Regulator
      3. 6.3.3 Low-Side Current Sense Amplifiers
        1. 6.3.3.1 Unidirectional Current Sense Operation
        2. 6.3.3.2 Bidirectional Current Sense Operation
      4. 6.3.4 Gate Driver Shutdown
        1. 6.3.4.1 DRVOFF Gate Driver Shutdown
        2. 6.3.4.2 Soft Shutdown Timing Sequence
      5. 6.3.5 Active Short Circuit
      6. 6.3.6 Gate Driver Protective Circuits
        1. 6.3.6.1  GVDD Undervoltage Lockout (GVDD_UV)
        2. 6.3.6.2  GVDD Overvoltage Fault (GVDD_OV)
        3. 6.3.6.3  VDRAIN Undervoltage Fault (VDRAIN_UV)
        4. 6.3.6.4  VDRAIN Overvoltage Fault (VDRAIN_OV)
        5. 6.3.6.5  VCP Undervoltage Fault (CP_UV)
        6. 6.3.6.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.6.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.6.8  MOSFET VGS Monitoring Protection
        9. 6.3.6.9  Shunt Overcurrent Protection (SNS_OCP)
        10. 6.3.6.10 Thermal Shutdown (OTSD)
        11. 6.3.6.11 Thermal Warning (OTW)
        12. 6.3.6.12 OTP CRC
        13. 6.3.6.13 SPI Watchdog Timer
        14. 6.3.6.14 Off State Diagnostic
    4. 6.4 Fault Detection and Response Summary Table (Fault Table)
    5. 6.5 Device Functional Modes
      1. 6.5.1 Gate Driver Functional Modes
        1. 6.5.1.1 Sleep Mode
        2. 6.5.1.2 Standby Mode
        3. 6.5.1.3 Active Mode
    6. 6.6 Programming
      1. 6.6.1 SPI
      2. 6.6.2 SPI Format
      3. 6.6.3 SPI Format Diagrams
  8. 7 Register Maps
    1. 7.1 STATUS Registers
    2. 7.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information

6.3.6.14 Off State Diagnostic

The device integrates a current source and a switch between VDRAIN and SHx device pins and between SHx device pin and the device ground for each channel. The switches can be individually enabled and disabled via SPI register bits OSD_Hx and OSD_Lx. If OSD_Hx is 1b, the source current IPHD_SRC of SHx pin is enabled. If OSD_Lx is 1b, the sink current IPHD_SNK of SHx pin is enabled. When any of OSD_Hx and OSD_Lx register bits are set to 1, the VDS overcurrent detection flags, VDS_Hx and VDS_Lx, change from the fault detection flag to the status flag of VDS comparators. The combination of the integrated current sources and VDS status flags can be used for the phase diagnostics such as an open fault detection of motor load, without activating external MOSFETs.

Table 6-3 Off state diagnostics table
Fault condition OSD_HB OSD_LB VDS_HB VDS_LB VDS_HA VDS_LA
No Fault 1 0 0 1 0 1
0 1 1 0 1 0
Short to GND 1 0 1 0 1 0
0 1 1 0 1 0
Short to VBAT 1 0 0 1 0 1
0 1 0 1 0 1
Open Load 1 0 0 1 Anything other than VDS_xB response
0 1 1 0
Note: Table above assumes OSD_HA & OSD_LA are left as 0 for all tests.
DRV8762-Q1 Off State Diagnostic Figure 6-18 Off State Diagnostic