SLVSM33 September   2026 TPS7H6200-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN PVIN
      2. 8.3.2  Bootstrap Operation
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Enable
      5. 8.3.5  Start-Up and UVLO
      6. 8.3.6  Programmable Dead-Time
      7. 8.3.7  Current Sense
      8. 8.3.8  Over Temperature Protection (TSD)
      9. 8.3.9  Fault Reporting (FLTB)
      10. 8.3.10 PWM
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Enable Configuration
        2. 9.2.2.2 Dead Time Setting
        3. 9.2.2.3 FLTB / Controller Connection
        4. 9.2.2.4 Configuring Current Sense
          1. 9.2.2.4.1 Current Sense Accuracy
        5. 9.2.2.5 FET Thermal Impedance
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     54

3 Description

The TPS7H6200-SEP is a 15V e-mode GaN power-FET with integrated gate driver featuring tri-state PWM compatibility, integrated low side current sense, overtemperature protection, and overcurrent protection.

The GaN FET half-bridge die combines the high-side and low-side GaN FETs on one substrate, minimizing parasitic inductance. The device is asymmetrically sized for point-of-load voltage conversion, 1mΩ on the low side and 3mΩ on the high side, optimizing performance and efficiency for typical input to output conversion ratios. As a result, the TPS7H6200-SEP can achieve efficiencies exceeding 89.6% at a typical load of 20A.

Device Information
PART NUMBER(1) Grade Package(2)
TPS7H6200MVEJTNSP(3) SEP 49-pin WQFN-FCRLF
6.00mm × 6.00mm
Mass = 72.9mg
(1) For additional information, see Device Options Table
(2) Dimension and mass values are nominal
(3) Advance Information
TPS7H6200-SEP Typical Application Typical Application