SLVSM33 September   2026 TPS7H6200-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN PVIN
      2. 8.3.2  Bootstrap Operation
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Enable
      5. 8.3.5  Start-Up and UVLO
      6. 8.3.6  Programmable Dead-Time
      7. 8.3.7  Current Sense
      8. 8.3.8  Over Temperature Protection (TSD)
      9. 8.3.9  Fault Reporting (FLTB)
      10. 8.3.10 PWM
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Enable Configuration
        2. 9.2.2.2 Dead Time Setting
        3. 9.2.2.3 FLTB / Controller Connection
        4. 9.2.2.4 Configuring Current Sense
          1. 9.2.2.4.1 Current Sense Accuracy
        5. 9.2.2.5 FET Thermal Impedance
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     54

9.2.2.5 FET Thermal Impedance

The TPS7H6200-SEP incorporated GaN FETs are on a monolithic substrate and sized for wide VIN to VOUT point of load synchronous buck applications; therefore, the sizing of the FETs are not symmetrical. The low-side FET is three times larger than the high-side FET, this results in the high side FET having a thermal impedance that is three times larger than the low side.

Figure 9-3 and Figure 9-4 show the modeled thermal impedance of the low-side and high side FETs. This modeling represents the combined thermal impedance at thermal pads 45 and 46 for the low-side FET and pad 47 for the high side FET.

Also included are equivalent Foster network RC values that facilitate thermal simulations of the mission of the mission profile. In conjunction with electrical simulations the Foster network values establish a thermal domain. Include in the thermal domain the lumped thermal resistance and capacitance models associated PCB and heat sink thermal characteristics. Figure 9-5 gives a simplified example of how to implement Foster network parameters with external thermal resistances, including PCB and other application considerations.

TPS7H6200-SEP Low-Side Thermal Impedance
Equivalent RC thermal network parameters
1 2  3 4
Ri(mºC/W) 26.9 130 1.25 1,080
Ci(μF) 50 50 231.85 174.42
Figure 9-3 Low-Side Thermal Impedance
TPS7H6200-SEP High-Side Thermal Impedance
Equivalent RC thermal network parameters
1 2  3 4
Ri(mºC/W) 417 196 1.05 3,090
Ci(μF) 39.8 10 9.05 64.5
Figure 9-4 High-Side Thermal Impedance
TPS7H6200-SEP Foster Thermal RC Network Figure 9-5 Foster Thermal RC Network