SLVSM93 October   2026 TMUX4051-EP , TMUX4052-EP , TMUX4053-EP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information: TMUX405x
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 AC Performance Characteristics
    7. 5.7 Timing Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  Transition Time
    5. 6.5  Break-Before-Make
    6. 6.6  tON(EN) and tOFF(EN)
    7. 6.7  Propagation Delay
    8. 6.8  Charge Injection
    9. 6.9  Off Isolation
    10. 6.10 Crosstalk
    11. 6.11 Bandwidth
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Operation
      2. 7.3.2 Rail-to-Rail Operation
      3. 7.3.3 1.8V Logic Compatible Inputs
      4. 7.3.4 Device Functional Modes
      5. 7.3.5 Truth Tables
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curves
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.7.1 Layout Guidelines

Route high-speed signals using minimal vias and corners, which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around Th via to minimize the capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies.

  • Decouple the VDD and VSS pins with a 0.1µF capacitor, placed as close to the pin as possible. Verify that the capacitor voltage rating is sufficient.
  • Keep the input lines as short as possible.
  • Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.