SLVSM93 October   2026 TMUX4051-EP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information: TMUX405x
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 AC Performance Characteristics
    7. 5.7 Timing Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  Transition Time
    5. 6.5  Break-Before-Make
    6. 6.6  tON(EN) and tOFF(EN)
    7. 6.7  Propagation Delay
    8. 6.8  Charge Injection
    9. 6.9  Off Isolation
    10. 6.10 Crosstalk
    11. 6.11 Bandwidth
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Operation
      2. 7.3.2 Rail-to-Rail Operation
      3. 7.3.3 1.8V Logic Compatible Inputs
      4. 7.3.4 Device Functional Modes
      5. 7.3.5 Truth Tables
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curves
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TMUX4051-EP TMUX4052-EP TMUX4053-EP TMUX4051-EP DYY Package, 16-Pin SOT-23-THIN (Top View)Figure 4-1 TMUX4051-EP DYY Package, 16-Pin SOT-23-THIN (Top View)
Pin Functions - TMUX4051-EP
PINTYPE(1)DESCRIPTION(2)
NAMENO.
S41I/OSource pin 4. Signal path can be an input or output.
S62I/OSource pin 6. Signal path can be an input or output.
D3I/ODrain pin (common). Signal path can be an input or output.
S74I/OSource pin 7. Signal path can be an input or output.
S55I/OSource pin 5. Signal path can be an input or output.
EN6IActive low logic enable. When this pin is high, all switches are turned off. Section 10 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low.
VSS7PNegative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VSS and GND.
GND8PGround (0V) reference
A29IAddress line 2. Section 10 provides information about how A2 controls the switch configuration.
A110IAddress line 1. Section 10 provides information about how A1 controls the switch configuration.
A011IAddress line 0. Section 10 provides information about how A0 controls the switch configuration.
S312I/OSource pin 3. Signal path can be an input or output.
S013I/OSource pin 0. Signal path can be an input or output.
S114I/OSource pin 1. Signal path can be an input or output.
S215I/OSource pin 2. Signal path can be an input or output.
VDD16PPositive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 7.3.4.
TMUX4051-EP TMUX4052-EP TMUX4053-EP TMUX4052-EP DYY Package, 16-Pin SOT-23-THIN (Top View) Figure 4-2 TMUX4052-EP DYY Package, 16-Pin SOT-23-THIN (Top View)
Table 4-1 Pin Functions - TMUX4052-EP
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S0B 1 I/O Source pin 0 of mux B. Signal path can be an input or output
S2B 2 I/O Source pin 2 of mux B. Signal path can be an input or output.
DB 3 I/O Drain pin (common) of mux B. Signal path can be an input or output.
S3B 4 I/O Source pin 3 of mux B. Signal path can be an input or output.
S1B 5 I/O Source pin 1 of mux B. Signal path can be an input or output.
EN 6 I Active low logic enable. When this pin is high, all switches are turned off. Section 10 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low.
VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VSS and GND.
GND 8 P Ground (0V) reference
A1 9 I Address line 1. Section 10 provides information about how A1 controls the switch configuration.
A0 10 I Address line 0. Section 10 provides information about how A0 controls the switch configuration.
S3A 11 I Source pin 3 of mux A. Signal path can be an input or output.
S0A 12 I/O Source pin 0 of mux A. Signal path can be an input or output.
DA 13 I/O Drain pin (common) of mux A. Signal path can be an input or output.
S1A 14 I/O Source pin 1 of mux A. Signal path can be an input or output.
S2A 15 I/O Source pin 2 of mux A. Signal path can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
TMUX4051-EP TMUX4052-EP TMUX4053-EP TMUX4053-EP DYY Package, 16-Pin SOT-23-THIN (Top View) Figure 4-3 TMUX4053-EP DYY Package, 16-Pin SOT-23-THIN (Top View)
Table 4-2 Pin Functions - TMUX4053-EP
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S2B 1 I/O Source pin B of switch 2. Signal path can be an input or output.
S2A 2 I/O Source pin A of switch 2. Signal path can be an input or output.
S3B 3 I/O Source pin B of switch 3. Signal path can be an input or output.
D3 4 I/O Drain pin (common) of switch 3. Signal path can be an input or output.
S3A 5 I/O Source pin A of switch 3. Signal path can be an input or output.
EN 6 I Active low logic enable. When this pin is high, all switches are turned off. Section 10 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low.
VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VSS and GND.
GND 8 P Ground (0V) reference
SEL3 9 I Logic control select pin 3. Section 10 provides controls switch 3 configuration
SEL2 10 I Logic control select pin 2.Section 10 provides controls switch 2 configuration
SEL1 11 I Logic control select pin 1.Section 10 provides controls switch 1 configuration
S1A 12 I/O Source pin A of switch 1. Signal path can be an input or output.
S1B 13 I/O Source pin B of switch 1. Signal path can be an input or output.
D1 14 I/O Drain pin (common) of switch 1. Signal path can be an input or output.
D2 15 I/O Drain pin (common) of switch 2. Signal path can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.