SLVSMQ2 July   2026 DLPC8545 , DLPC8555

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     6
    2. 4.1  Initialization, Board Level Test, and Debug
    3. 4.2  V-by-One Interface Input Data and Control
    4. 4.3  DSI Input Data and Clock
    5. 4.4  DMD SubLVDS Interface
    6. 4.5  DMD Reset and Low Speed Interfaces
    7. 4.6  Flash Interface
    8. 4.7  Peripheral Interfaces
    9. 4.8  GPIO Peripheral Interface
    10. 4.9  Clock and PLL Support
    11. 4.10 Power and Ground
    12. 4.11 I/O Type Subscript Definition
    13. 4.12 Internal Pullup and Pulldown Characteristics
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2.     21
    3. 5.2  ESD Ratings
    4. 5.3  Recommended Operating Conditions
    5. 5.4  Thermal Information
    6. 5.5  Power Electrical Characteristics
    7. 5.6  Pin Electrical Characteristics
    8. 5.7  DMD SubLVDS Interface Electrical Characteristics
    9.     28
    10. 5.8  DMD Low Speed Interface Electrical Characteristics
    11.     30
    12. 5.9  V-by-One Interface Electrical Characteristics
    13. 5.10 USB Electrical Characteristics
    14.     33
    15. 5.11 System Oscillator Timing Requirements
    16.     35
    17. 5.12 Power Supply and Reset Timing Requirements
    18.     37
    19. 5.13 V-by-One Interface General Timing Requirements
    20.     39
    21. 5.14 Flash Interface Timing Requirements
    22.     41
    23. 5.15 Source Frame Timing Requirements
    24.     43
    25. 5.16 Synchronous Serial Port Interface Timing Requirements
    26.     45
    27. 5.17 I2C Interface Timing Requirements
    28. 5.18 Programmable Output Clock Timing Requirements
    29. 5.19 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    30.     49
    31. 5.20 DMD Low Speed Interface Timing Requirements
    32.     51
    33. 5.21 DMD SubLVDS Interface Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Input Sources
      2. 6.3.2 V-by-One Interface
      3. 6.3.3 DMD (SubLVDS) Interface
      4. 6.3.4 Serial Flash Interface
      5. 6.3.5 GPIO Supported Functionality
        1.       62
      6. 6.3.6 Debug Support
  8. 7 Power Supply Recommendations
    1. 7.1 System Power-Up and Power-Down Sequence
    2. 7.2 DMD Fast Park Control (PARKZ)
    3. 7.3 Power Supply Management
    4. 7.4 Hotplug Usage
    5. 7.5 Power Supplies for Unused Input Source Interfaces
  9. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Layout Guideline for DLPC8545, or DLPC8555 Reference Clock
        1. 8.1.1.1 Recommended Clock Oscillator Configuration
      2. 8.1.2 V-by-One Interface Layout Considerations
      3. 8.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 8.1.4 Power Supply Layout Guidelines
    2. 8.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Device Nomenclature
      1. 9.5.1 Device Markings
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
      1. 9.8.1 Video Timing Parameter Definitions
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.15 Source Frame Timing Requirements

PARAMETER (1)(7) MIN TYP MAX UNIT
tp_vsw VSYNC Active Pulse Width 50% reference points 1 10 lines
tp_vbp Vertical back porch (VBP) 50% reference points 2(2)(3) 72(2)(3) lines
tp_vƒp Vertical front porch (VFP)  50% reference points  1(2)(3)  8(2)(3) lines
tp_tvb Total vertical blanking (TVB)  50% reference points 30(2)(3) 90(2)(3) lines
tp_hsw HSYNC Active Pulse Width 50% reference points 3(4)(5) 88(4)(5) PCLKs
tp_hbp Horizontal back porch (HBP) 50% reference points 4(4)(5) 296(4)(5) PCLKs
tp_hfp Horizontal front porch (HFP)  50% reference points 7(4)(5) 176(4)(5) PCLKs
tp_thb Total horizontal blanking (THB)(10) 50% reference points 80(4)(5) 560(4)(5) PCLKs
APPL Active Pixels per Line(8)

960

(6)(9)

1920

(6)

1920

 Pixels
ALPF Active Lines per Frame

1080

(6)(9)		 2160(6) 2160 Lines
(1) The requirements in the table apply to all external sources of a 4K DLP display system.
(2) Total Vertical Blanking: The sum of VBP + VFP + VS.
(3) The vertical blanking required (per TVB) can be allocated as desired as long as the VFP and VBP minimum values are met.
(4) Total Horizontal Blanking: The sum of HBP + HFP + HS.
(5) The horizontal blanking required (per THB) can be allocated as desired as long as the HFP, HBP and HS minimum values are met.
(6) The min APPL and ALPF must be met, for the non-standard timing to keep the minimum pixel clock and blanking requirements. The defined minimum is based on a standard 720p input source as an reference for V-by-One.
(7) Video parameter limits set in compliance to CVT 1.2 standard including reduced blanking 4K 60Hz timing. 
(8) The APPL must be a multiple of incoming number of lanes (1, 2, 4, 8) when using V-by-One video input. 
(9) V-by-One is only capable of supporting video sources down to 1280x720.
(10) The total horizontal blanking divided by the number of lanes used in the video source must be a whole number. If the blanking fluctuates by more than two pixels, the source does not lock.