If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the SAFE state.

If an OFF request occurs, such as the TPS65941515 ENABLE pin being pulled low, the same power down sequence occurs, except the PMIC goes to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the SAFE state. The power sequence for both of these events is shown in Figure 6-3.

Both the TO_SAFE_ORDERLY and TO_STANDBY sequences set the SPMI_LP_EN and FORCE_EN_DRV_LOW bits.

At the end of the TO_SAFE_ORDERLY sequence, the PMIC waits approximately 16 ms before executing the following instructions:

// Clear AMUXOUT_EN and CLKMON_EN and set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// Reset all BUCKs
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0

The resetting of the BUCK regulators is done in preparation to transitioning to the SAFE_RECOVERY state. Transitioning to the SAFE_RECOVERY state means that the PMIC leaves the mission state. The SAFE_RECOVERY state is where the recovery mechanism increments the recovery counter and determine if the recovery count threshold (see Table 5-10) was achieved before attempting to recover.

At the end of the TO_STANDBY sequence, the TPS65941515 device waits approximately 16 ms before executing the same AMUXOUT_EN, CLKMON_EN, and LPM_EN bit manipulations. The BUCKs are not reset. After these instructions, the PMIC performs an additional check to determine if the LP_STANDBY_SEL (see Table 5-10) is true. If true, then the PMIC enters the LP_STANDBY state and leave the mission state. If the LP_STANDBY_SEL is false, then the PMIC remains in the mission state defined by STANDBY in Section 6.1.