SLVUCD4 November   2022 TPS6594-Q1

 

  1.   PDN-2A User's Guide for Powering DRA821 with TPS65941515-Q1 PMIC
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 TO_ACTIVE
      5. 6.3.5 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8References

3.1 Power Mapping

Figure 3-1 shows the power mapping between the TPS65941515-Q1 PMIC and peripheral regulators to power the processor and associated accessories. In this configuration, the PMIC and additional resources use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the PMIC, allowing voltage monitoring of the input supply to the system.

This PDN uses five discrete power components with four being required and one is optional depending upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply 3.3 V to processor I/O domains. The third discrete device is a TPS274501-Q1 LDO is used to supply power in low-power retention mode. The fourth discrete device is a TLV73318-Q1 LDO which supplies the LPDDR4 SDRAM component with required 1.8V supply. The last discrete power component is an optional TLV73318-Q1 LDO that can be used if an end product uses a high security processor type and desires the capability to program EFUSE values on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.

Figure 3-1 Power Connections

  • * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS
  • ** VPP_EFUSE_1V8, is optional

Table 3-1 identifies which power resources are required to support different system features. In the Active SoC column, there is an additional option for including or excluding the VPP_x(EFUSE) rail.

Table 3-1 PDN Power Mapping and System Features
Power Mapping System Features(1)
Device Power Resource Power Rails Processor and Memory Domains Active SoC

GPIO Retention

 DDR Retention SD Card USB Interface
TPS65941515-Q1 BUCK12 VDD_CPU_AVS VDD_CPU R

BUCK34

VDD_CORE_0V8

 VDD_MCU,

VDDA_SERDES

 R
BUCK5 VDD_DDR_1V1

VDDS_DDR

 R

R

Mem: LPDDR4_VDD2 and VDDQ
LDO1 VDD_IO_1V8 VDDS_MMC0, VDDSHVx_MCU(1.8V) R

Mem: VCC
LDO2 VDD_RAM_0V85

VDDAR_MCU, VDDAR_CPU/CORE

 R
LDO3 VDA_DPLL_0V8 VDDA_0P8_PLLs/DLLs R
LDO4 VDA_LN_1V8 VDDA_x(1.8V) R
TPS22965-Q1 Load Switch-A VDD_IO_3V3 VDDSHVx_MCU (3.3 V),

VDDSHV0, VDDSHV5

 R

R

R

Mem: EMMC VCC
TPS22965-Q1 Load Switch-B VDD_GPIORET_3V3 VDDSHV0-4,VDDSHV6 (3.3 V) R

R

TPS74501P-Q1

LDO-A

VDD_WK_0V8

VDDSHV2

R

R
TLV73318P-Q1 LDO-B

VDD1_LPDDR4_1V8

Mem: LPDDR4_VDD1

R
TLV73318P-Q1 LDO-C

VPP_EFUSE_1V8

VPP_x(EFUSE)

O
(1) 'R' is required and 'O' is optional.