SLVUCK4A march   2023  – july 2023 TPS25948

 

  1.   1
  2.   TPS25948EVM: Evaluation Module for TPS25948 eFuse
  3.   Trademarks
  4. 1Introduction
    1. 1.1 EVM Features
    2. 1.2 EVM Applications
  5. 2Description
  6. 3Schematic
  7. 4General Configurations
    1. 4.1 Physical Access
    2. 4.2 Test Equipment and Setup
      1. 4.2.1 Power Supplies
      2. 4.2.2 Meters
      3. 4.2.3 Oscilloscope
      4. 4.2.4 Loads
  8. 5Test Setup and Procedures
    1. 5.1 Hot-Plug Test
    2. 5.2 Overcurrent Test
    3. 5.3 Output Hot-Short Test
    4. 5.4 Wakeup into Short Test
    5. 5.5 Overvoltage Test
    6. 5.6 Priority Power Mux Test
  9. 6EVAL Board Assembly Drawings and Layout Guidelines
    1. 6.1 PCB Drawings
  10. 7Bill Of Materials (BOM)
  11. 8Revision History

4.1 Physical Access

Table 4-1 lists the TPS25948EVM eFuse evaluation board input and output connector functionality. Table 4-2 and Table 4-3 describe the test point availability and the jumper functionality. Table 4-4 describes the function of signal LEDs.

Table 4-1 Input and Output Connector Functionality
ChannelConnectorLabelDescription
CH1J2VIN1(+), PGND(–)Input of CH1
J1VOUT1(+), PGND(–)Output of CH1
CH2J12VIN2(+), PGND(–)Input of CH2
J11VOUT2(+), PGND(–)Output of CH2
Table 4-2 Test Points Description
ChannelTest PointsLabelDescription
CH1TP1VIN1CH1 input voltage
TP2VOUT1CH1 output voltage
TP4EN/UVLO1CH1 EN/UVLO signal
TP5OVLO1CH1 OVLO signal
TP6ITIMER1CH1 ITIMER signal
TP7dVdt1CH1 output voltage ramp control
TP8ILM1CH1 current limit and monitor signal
TP10FLTb1CH1 fault signal
TP9SPLYGD1CH1 supply good signal
TP13GND1CH1 IC GND signal
CH2TP14VIN2CH2 input voltage
TP15VOUT2CH2 output voltage
TP16EN/UVLO2CH2 EN/UVLO signal
TP17OVLO2CH2 OVLO signal
TP18ITIMER2CH2 ITIMER signal
TP19dVdt2CH2 output voltage ramp control
TP20ILM2CH2 current limit and monitor signal
TP22RCBCTRL2CH2 reverse current blocking control signal
TP21SPLYGD2CH2 supply good signal
TP25GND2CH2 IC GND signal
CH1 & CH2TP3VCC_EXTExternal VCC voltage point for CH1 and CH2
TP11,TP12,TP23,TP24PGNDCommon Power GND for CH1 and CH1
Table 4-3 Jumper Descriptions and Default Positions
ChannelJumperLabelDescriptionDefault Jumper Position
CH1J5dVdt11-2 position sets the output slew rate to 1.5 mV/us3-4
3-4 position sets the output slew rate to 0.5 mV/us
5-6 position sets the output slew rate to 0.23 mV/us
J6ILM11-2 position sets the current limit to 1 A7-8
3-4 position sets the current limit to 3 A
5-6 position sets the current limit to 4.5 A
7-8 position sets the current limit to 9 A
J8ITIMER11-2 position sets the transient current blanking period to 170 us3-4
3-4 position sets the transient current blanking period to 1.7 ms
5-6 position sets the transient current blanking period to 17 ms
J7OVLO11-2 position sets input OVLO threshold at 13.8 V

3-4

3-4 position sets input OVLO threshold at 16.4 V
5-6 position sets input OVLO threshold at 21.5 V
J4OVLO1_VIN1Connects OVLO pin to VIN resistor ladder1-2
J3UVLO1_VIN1Connects UVLO pin to VIN resistor ladder1-2
J15dVdt21-2 position sets the output slew rate to 1.5 mV/us3-4
3-4 position sets the output slew rate to 0.5 mV/us
5-6 position sets the output slew rate to 0.23 mV/us
J16ILM21-2 position sets the current limit to 1 A7-8
3-4 position sets the current limit to 3 A
5-6 position sets the current limit to 4.5 A
CH27-8 position sets the current limit to 9 A
J19ITIMER21-2 position sets the transient current blanking period to 170 us3-4
3-4 position sets the transient current blanking period to 1.7 ms
5-6 position sets the transient current blanking period to 17 ms
J18OVLO21-2 position sets input OVLO threshold at 13.8 V3-4
3-4 position sets input OVLO threshold at 16.4 V
5-6 position sets input OVLO threshold at 21.5 V
J20OVLO2_SPLYGD1

1-2 Position connects the SPLYGD1 with OVLO2. Use this setting for Power Muxing operation of U1 and U2

2-3

2-3 position connects OVLO2 to VIN resistor ladder

J21UVLO2_SPLYGD11-2 Position connects the SPLYGD1 with EN/UVLO2. Use this setting for parallel operation of U1 and U22-3
2-3 position connects EN/UVLO2 to VIN resistor ladder
J14OVLO2_VIN2Connects OVLO pin to VIN resistor ladder1-2
J13UVLO2_VIN2Connects UVLO pin to VIN resistor ladder1-2
J17RCBCTRL2

Connects RCBCTRL to GND to disable reverse current blocking

Open
CH1 & CH2J9VCC connection

CH-1,2

2-3 position connects onboard generated voltage, VCC as reference for digital signals of U1 and U22-3
Table 4-4 LED Descriptions
LED Description
D1 When ON, indicates that SPLYGD is asserted for channel 1
D3 When ON, indicates that FLTb is asserted for channel 1
D7 When ON, indicates that SPLYGD is asserted for channel 2