SLVUD28 March   2025 TPS7H5020-SEP , TPS7H5020-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 EVM Connections and Test Points
    2. 2.2 Best Practices
  8. 3Implementation Results
    1. 3.1 Evaluation Setup
    2. 3.2 Startup
    3. 3.3 Shutdown
    4. 3.4 Output Voltage Ripple
    5. 3.5 Load Step
    6. 3.6 Frequency Response
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Compliance Information
  11. 6Additional Information
    1. 6.1 Trademarks
  12. 7Related Documentation

2.1 EVM Connections and Test Points

Figure 2-1 shows which terminal is the positive and negative on J11. Connect the positive input voltage to the positive terminal and GND to negative terminal.

TPS7H5020EVM J1 Input Terminal Figure 2-1 J1 Input Terminal

Table 2-1 is a list of connections on the board.

Table 2-1 EVM Board Connections
Reference Designator Function

J1

VIN

Power output connector

J2

VOUT

Power input connectors

J3

GND

J4

VOUT

Compact probe tip connector

J5

SW

TP1

VIN

Test point

TP2

VOUT

TP3

VIN

TP4

VOUT

TP5

BODE

TP6

EN

TP7

VLDO

TP8

SYNC

TP9

SS

TP10

COMP

TP11

Gate

Probe tip test point

TP12

CS_ILIM

Test point

TP13

VSENSE

TP14, TP15, TP16, TP17, TP18, TP19

GND