SLVUDA9 October   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 I/O Information
    2. 2.2 Jumper Information
    3. 2.3 Equipment
    4. 2.4 Hardware Setup
  9. 3Software
    1. 3.1 Software Setup
    2. 3.2 Test Procedure
      1. 3.2.1 Initial Power Up
      2. 3.2.2 I2C Register Communication Verification
      3. 3.2.3 Forward/Charge/Sink Mode Verification
      4. 3.2.4 Reverse/OTG/Source Mode Verification
      5. 3.2.5 Helpful Tips
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
      1. 4.2.1 PCB Layout Guidelines
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1.     Trademarks
  12. 6Revision History

3.2.4 Reverse/OTG/Source Mode Verification

Use the following steps for reverse/OTG/source mode verification:

  1. Turn off and disconnect PS #1.
  2. Set Load #1, the battery simulator, to 7V and 2A current limit.
    Note: If Load #1 connected from J3 BAT to GND is not a four quadrant supply, then remove Load #1 and use PS #1, replace with 7V, 2A current limit.
  3. In the EVM software on the 16-bit tab, confirm that VIN_REV, the reverse mode regulation voltage, is set to 5000 mV and IIN_REV, the reverse mode output current limit, is set to 1000mA.
  4. In the EVM software in the 8 Bit Chip Single-bit section
    1. Uncheck EN_BAT_DETECT
    2. Check EN_REV
  5. Connect disabled Load #2 across J2 VPWR and PGND
  6. Set Load #2 to 500mA constant current load (or 10Ω constant resistance load) and the turn on the load.
  7. To confirm the reverse regulation,
    • Measure→ VBUS = 5.0V ± 155mV
  8. Turn off and disconnect the power supply.
  9. Remove Load #2 from the connection.